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[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 1 - 1. general description the ak449 2 is a new generation premium 32 - bit 2ch da c with velvet sound tm technology , achieving industrys leading level low distortion characteristics. the osr - doubler technology establi sh es low power consumption and low dis tortion characteristics. moreover, the ak449 2 has six types of 32 - bit digital filters, realizing simple and flexible sound tuning in wide range of applications. the ak449 2 accepts up to 768khz pcm data and 11 . 2 mhz dsd data, ideal for a high - resolution audi o source playback that are becoming widespread in smartphone , portable audio player etc . application: smart cellular phones, ic - recorder s , bluetooth headphone s , cd/sacd players, network audios , usb dac s, usb headphone s , sound plate s /bar s , hd audio/voice c onference systems, av receivers 2. features ? thd+ n: - 1 1 5 db ? dr, s/n: 1 27 db ( 2 vrms output ) ? 128 times over sampling ? sampling rate : 8 khz ? ? 32 - bit 8 x digital filter - short delay sharp roll - off, gd=6. 0 /fs , ripple: ? - s hort delay slow roll - off , gd= 5.0 /fs - sharp roll - off - slow roll - off - low - dispersion short delay filter - super slow roll - off ? high tolerance to clock jitter ? low distortion differential output ? 2.8 mhz, 5.6 mhz , 11.2 mhz dsd input support - filter 1 (fc = 39 khz, 2.8 mhz mode) - filter 2 (fc = 76 khz, 2.8 mhz mode) ? digital de - emphasis for 32, 44.1 and 48khz sampling ? soft mute ? digital attenuator (255 levels and 0.5db step + mute ) ? mono mode ? external digital filter interface ? audio i/f format : 24/32 bit m sb justified , 16/20/24/32 bit l sb justified , i 2 s, dsd , tdm ? master clock 8 khz ~ 32 khz: 256 fs or 384 fs or 512 fs or 768 fs or 1024 fs or 1152 fs 8 khz ~ 54 khz: 256 fs or 384 fs or 512 fs or 768 fs 8 khz ~ 108 khz: 256 fs or 384 fs 108 khz ~ 216 khz: 1 28 fs or 192 fs ~ 384 khz: 32 fs or 48 fs or 64 fs or 96 fs ~ 7 68 khz: 16 fs or 32 fs or 48 fs or 64 fs ? 3 - wire, i 2 c - bus interface ak449 2 quality oriented 32 - bit 2ch dac
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 2 - ? power supply : (by internal ldo)tvdd =avdd= 3.0 ? ? ? ? ? operational temperature rnage : ? 40 ? ? digital input level : cmos ? package : 96 - pin wlcsp
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 3 - 3. table of contents 1. general description ................................ ................................ ................................ ........................ 1 2. features ................................ ................................ ................................ ................................ .......... 1 3. table of contents ................................ ................................ ................................ ............................ 3 4. block diagram ................................ ................................ ................................ ................................ . 5 5. pin configurations and functions ................................ ................................ ................................ ... 6 pin configurations ................................ ................................ ................................ .............................. 6 pin functions ................................ ................................ ................................ ................................ ..... 7 handling of unused pin ................................ ................................ ................................ ................... 10 6. absolute maximum ratings ................................ ................................ ................................ .......... 11 7. recommended operating conditions ................................ ................................ .......................... 11 8. electrical charac teristics ................................ ................................ ................................ .............. 12 analog characteristics ................................ ................................ ................................ ..................... 12 sharp roll - off filter characteristics ................................ ................................ ................................ 15 slow roll - off filter characteristics ................................ ................................ ................................ .. 17 short de lay sharp roll - off filter characteristics ................................ ................................ ............ 19 short delay slow roll - off filter characteristics ................................ ................................ .............. 21 low - dispersion short delay filter characteristics ................................ ................................ ........... 23 dsd filter characteristics ................................ ................................ ................................ ................ 25 dc characteristics ................................ ................................ ................................ ........................... 25 switching characteristics ................................ ................................ ................................ ................. 26 timing diagram ................................ ................................ ................................ ................................ 31 9. functional descriptions ................................ ................................ ................................ ................. 36 d/a conversion mode (pcm mode, dsd mode, exdp mode) ................................ ...................... 38 d/a conversion mode switching timing ................................ ................................ ......................... 38 system clock ................................ ................................ ................................ ................................ ... 40 audio interface format ................................ ................................ ................................ .................... 49 digital filter ................................ ................................ ................................ ................................ ...... 61 de - emphasis filter (pcm mode) ................................ ................................ ................................ ..... 62 output volume (pcm mode, dsd mode, exdf mode) ................................ ................................ .. 62 gain adjustment function (pcm mode, dsd mode, exdf mode) ................................ ................ 63 zero detection (pcm mode, dsd mode, exdf mode) ................................ ................................ .. 64 l/r channel output signal select, phase inversion function (pcm mode, dsd mode, exdf mode) ................................ ................................ ................................ ................................ .............................. 65 dsd signal full scale (fs) detection ................................ ................................ ............................. 66 soft mute operation (pcm mode, dsd mode, exdf mode) ................................ ......................... 68 ldo ................................ ................................ ................................ ................................ .................. 69 shutdown switch ................................ ................................ ................................ .............................. 69 power up/down function ................................ ................................ ................................ ................ 70 power - off/reset function ................................ ................................ ................................ ............. 74 synchronize function (pcm mode, exdf mode) ................................ ................................ ........... 77 register control interface ................................ ................................ ................................ ................ 79 register map ................................ ................................ ................................ ................................ .... 83 10. recommended external circuits ................................ ................................ ................................ .. 94 1. grounding and power supply decoupling ................................ ................................ ....................... 95 2. voltage reference ................................ ................................ ................................ ............................ 95 3. ana log output ................................ ................................ ................................ ................................ ... 95 4. connection with ak8157a ................................ ................................ ................................ ................ 97 5. connection with ak4205 ................................ ................................ ................................ .................. 98 11. package ................................ ................................ ................................ ................................ ........ 99 outline dimensions ( 96 - pin wlcsp ) ................................ ................................ .............................. 99 material & lead finish ................................ ................................ ................................ ..................... 99
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 4 - marking ................................ ................................ ................................ ................................ ............. 99 12. ordering guide ................................ ................................ ................................ ........................... 100 ordering guide ................................ ................................ ................................ ............................... 100 13. revesion history ................................ ................................ ................................ ......................... 100 important notice ................................ ................................ ................................ ............................ 101
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 5 - 4. block diagram figure 1 . block diagram mclk s data/dinl/dsdl smute/csn bi ck /bck/dclk sd/ cclk/scl slow/cdti/sda vssr vddr pdn avdd scf scf clock divider dvss dvdd sslow/wck acks/ cad1 psn dif 0/ dzfl dif2/ cad0 vssl vddl vcml aoutrn vcmr vrefhl vrefll vreflr vrefhr avss aoutlp aoutln aoutrp pcm data interface dsd data interface external df interface control register vref lr ck /dinr/dsdr dif 1/ dzf r datt soft mute ? ? ? modulator v olume by pass dsdd bit 1 normal path dsdd bit 0 oscillator tvdd tdm1 dchain ldo ldoe tdm0/dclk dem0/dsdl gain/dsdr tdmo invr teste hload /i2c extr iref dsd filter de - emphasis & interpolator mclk stop detection
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 6 - 5. pin configurations and functions pin configurations 10 vddr vssr vssr vssl vssl vddl 9 aoutrn aoutrp vddr vddr vssr vssl vddl vddl aoutlp aoutln 8 vreflr vcmr nc nc nc nc nc nc vcml vrefll 7 vreflr nc nc nc nc nc nc nc nc vrefll 6 vrefhr nc nc nc nc nc nc nc nc vrefhl 5 vrefhr teste nc nc nc nc n c nc extr vrefhl 4 invr dchain nc nc nc nc nc nc avss avdd 3 tdm0/ dclk tdm1 nc psn nc nc nc ldoe mclk dvdd 2 acks/ cad1 gain/ dsdr hload/ i2c dif2/ cad0 sd/ cclk/ scl tdmo sslow/ wck pdn tvdd dvss 1 nc dem0/ dsdl dif1/ dzfr dif0/ dzfl slow/ cdti/ sda smute/ csn lrck/ dinr/ dsdr sdata/ dinl/ dsdl bick/ bck/ dclk nc a b c d e f g h j k figure 2 . pin configurations the exposed pad on the bottom surface of the package must be connected to vss . ak4 492 top view k lrck 18 j h g f e d c b a 1 2 3 4 5 6 7 8 9 10
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 7 - pin functions no. pin name i/o protection diode function a2 acks i tvdd/dvss auto setting mode select pin in pin control mode (psn pin = h) l: manual setting mode, h: auto setting mode l) (psn pin=h) psn pin=l, 0) (psn pin=h) l, 0) h) l:output level vpp, h: output level 3.75 l, 0) h) l) (internal pull - down pin) c2 hload i tvdd/dvss heavy load mode enable pin in pin control mode (psn pin = h) l:normal drive mode, h: heavy load drive mode l) l: 3 wire serial mode, h: i 2 c - bus mode c9 vddr - - rch analog power supply pin c1 0 vddr - - rch analog power supply pin d1 dif0 i tvdd/dvss digital input format 0 pin in pin control mode (psn pin = h) (psn pin=l) h) l) l: register control mode, h: pin control mode
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 8 - no. pin name i/o protection diode function e1 slow i h) l, i2c pin l) l, i2c pin h) h) l, i2c pin l) l, i2c pin h) h) when this pin is changed to h, soft mute cycle is initiated. when returning l, the output mute releases. l, i2c pin l) l, i2c pin h) 1) h) l) 1) when at l, the ak4492 is in power internal ldo enable pin. l: disable, h: enab 1) l: (dvdd) ~ 3.6 h: 3.0 ~ 3.6v k(1
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 9 - note 1 . it is recommended to use a r esistor with 0.1% absolute error in fs auto detect mode . note 2 . all input pins except for internal pull - up/down pins must not be left floating. note 3 . reset by pdn pin when changing control mode(pin control ? register control) by psn pin . note 4 . pcm mode, dsd mode and exdf mode are controlled by register settings. no. pin name i/o protection diode function k2 dvss - - digital ground pin k3 dvdd o - (ldoe pin = h) ldo output pin, this pin should be connected to dvss with 1.0 f. this pin is inhibited to connect other devices. - (ld oe pin = l) 1.8 v power input pin k4 avdd - - analog power supply pin. ldoe pin = l: (dvdd) ~ 3.6 v / ldoe pin = h: 3.0 ~ 3.6 v k5 vrefhl i vddl/vssl lch high level voltage reference input pin k6 vrefhl i vddl/vssl lch high level voltage referenc e input pin k7 vrefll i vddl/vssl lch low level voltage reference input pin k8 vrefll i vddl/vssl lch low level voltage reference input pin k9 aoutln o vddl/vssl lch negative analog output pin
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 10 - handling of unused pin unused i/o pins must be connected appropr iately. (1) pin control mode (pcm mode only ) classification pin name status analog aoutlp, aoutln, aoutrp, aoutrn open teste connect to a vss or open (2) resister control mode 1. pcm mode 2. dsd mode dsdpath bit = 0 dsdpath bit = 1 classification pin name status analog aoutlp, aoutln, aoutrp, a outrn open teste connect to a vss or open digital dclk, dsdl, dsdr, wck, tdm1, dchain, invr connect to d vss tdmo, dzfr, dzfl open csn connect to d vss (i2c pin = h) (i2c pin = h) k) (i2c pin = h) (i2c pin = h)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 11 - 6. absolute maximum ratings ( avss = dvss = vssl = vssr = vrefll = vreflr = 0 v ; note 5 ) parameter symbol m in . m ax . unit power supplies: di gital i/o digital core clock in eterface analog |avss ? ? ? ? ? ? ? ? ? ? ? ? warning: operation at or beyond these limits may result in permanent damage to the device. normal operation i s not guaranteed at these extremes. 7. recommended operating conditions ( avss = dvss = vssl = vssr = vrefll = vreflr = 0 v ; note 5 ) parameter symbol m in . t yp . m ax . unit power supplies voltage reference ( note 8 ) h voltage reference l voltage reference vrefhl/r vrefll/r vddl/r - 0.5 - - vssl/r vddl/r - v v note 5. all voltages with respect to ground. note 8 . the analog output voltage scales with the voltage of (vrefhl/r ? vrefll/r). note 9 . tvdd and avdd must be connected to the same ground plane and powered up at the same time. when not using the ldo (ldoe pin = l ), all power supplies (dvdd (1.8v), tvdd and avdd (3.3v) and vddl/r (5v)) should be powered up at the same time or sequentially in the order of 3.3v (tvdd, avdd), 1.8v (dvdd) and 5v (vddl/r). note 10 . the internal ldo outputs dvdd (1.8v) when the ldoe pin = h . 3.3v ( tvdd and avdd) power supplies must be powered up before or at the same time with 5v (vddl/r) power supplies when the ldoe pin = h . * akm assumes no responsibility for the usage beyond the conditions in this data sheet.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 12 - 8. elect rical characteristics analog characteristics pcm m ode (ta = 25 ? c; ldoe pin = l, avdd = tvdd = dvdd = 1.8 v, avss = dvss = vssl/r = 0 v; vrefhl/r = vddl/r = 5.0 v, vrefll/r= 0v; input data = 24 bit; bick = 64 fs; signal frequency = 1 khz; sampling f requency = 44.1 khz; measurement bandwidth = 20 hz ~ 20 khz; 2 vrms output mode (gc[2:0] bit s = 000 or gain pin = l); heavy load drive mode = off(hload bit = 0 or hload pin = l); unless otherwise specified.) parameter m in . t yp . m ax . unit resoluti on - - 32 bit dynamic characteristics ( note 11 ) thd+n fs=44.1khz bw=20khz 0dbfs gc[2:0]= 000 l gc[2:0]= 100 h ? ? ? ? ? 000 l 100 h dc accuracy ( note 13 ) interchannel gain mismatch - 0.15 0.3 db gain drift - 20 - ppm/ ? gc[2:0]= 000 =l ( ? ? ? gc[2:0]= 100 or =h ( ? ? ? hload= 0 or pin=l ? hload= 1 or =h ? 000 or the gain pin = l is calculated by the following formula . aoutl/r (typ.@0d b) = (aout + ) ? (aout ? ) = ? 2.8vpp ? (vrefhl/r ? vrefll/r)/5. note 15 . the analog output voltage with 0dbfs input signal when gc[2:0] bits = 100 or the gain pin = h is calculated by the following formula. aoutl/r (typ.@0db) = (aou t + ) ? (aout ? ) = ? 3.75vpp ? (vrefhl/r ? vrefll/r)/5. note 16 . the l oad r esistance value with respect to ground. 10.3 system design analog output shows the circuits and the calculataion example. note 17 . the loa d capacitance value with respect to ground. analog characteristics are sensitive to capacitive load that is connected to the output pin. therefore the capacitive load must be minimized. note 18 . it is recommended to use a resistor wi th 0.1% absolute error for the output stage of the adding circuit.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 13 - (ta = 25 ? c; ldoe pin = l, avdd = tvdd = dvdd = 1.8 v, avss = dvss = vssl/r = 0 v; vrefhl/r = vddl/r = 5.0 v, vrefll/r = 0v; input data = 24 bit; bick = 64 fs; signal frequency = 1khz; sampling frequency = 44.1khz; 2 vrms output mode (gc[2:0] bits = 000 or gain pin = l); heavy load drive mode = off(hload bit= 0 or hload pin=l); unless otherwise specified.) power supplies parameter m in . t yp . m ax . unit power supply current normal operation (pdn pin = h) h l l l power down (pdn pin = l) ( ? in power down mode, t he psn pin = t vdd an d all other digital input pins including clock pins (mclk, bick and lrck) are held to dvss. note 20 . the dvdd pin becomes an output pin when the ldoe pin = h .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 14 - dsd m ode (ta = 25 ? c; ldoe pin = l , avdd = tvdd = dvdd = 1.8 v; avss = dvss = vssl/r = 0 v; vrefhl/r = vddl/r = 5.0 v, vrefll/r = 0 v; signal frequency = 1 khz; measurement bandwidth = 20 hz ~ 20 khz; external circuit: figure 74 ; 2 vrms output mode (gc[2:0] bits = 000 or gain pin = l ); unless otherwise specified.) parameter min. typ. max. unit dynamic characteristics thd+n ( note 21 ) dsd data stream : 2.8224 mhz 0db - - 111 - db dsd data stream : 5.6448 mhz 0db - - 112 - db dsd data stream : 11.2896 mhz 0db - - 107 - db s/n (a - weighted, normal path) ( note 21 ) dsd data stream : 2.8224 mhz digital0 digital0 digital0 dc accuracy output voltage (normal path) ( note 25 ) ? ? ? ( note 25 ) ? ? ? the peak level of dsd signal should be in the range of 25% ~ 75% d uty according to the sacd format book (scarlet book). note 23 . the output level is assumed as 0db when a 1khz 2 5% ~ 75% d uty sine wave is input. click noise may occur if the input signal exceeds 0db. note 24 . digital 0 is a digital zero code pattern ( 01101001 ) according to the sacd format book (scarlet book). note 25 . in case of gc[2:0] = 000 and dsdd bit = 1 , t he analog output voltage at input signal = 0db is following equation. aoutl/r ( typ.@0 db) = (aoutlp/rp) ? (aoutln/rn) = ? 2.5 vpp ? (vrefhl/r ? vrefll/r)/5 .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 15 - sharp roll - of f filter characteristics sharp roll - off filter characteristics (fs= 44.1 khz) (ta = - 40~85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7 ~ 1.98 v; normal speed mode; dem = off; sd bit or sd pin = 0, slow bit or slow pin = 0, sslow bi t or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency response ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? sharp roll - off filter characteristics (fs=96khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6v, dvdd = 1.7~1.98v ; double speed mode; dem = off; sd bit or sd pin = 0, slow bit or slow pin = 0 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency response ? ? ? ( note 26 ) sa 100 db group delay ( note 29 ) gd - 29.2 - 1/fs digital filter + scf ( note 26 ) frequency response: 0 ? sharp roll - off filter characteristics (fs=192khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v ; quad speed mode; dem = off; sd bit or sd pin = 0, slow bit or slow pin = 0 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency responce ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? ? 0.01db), sb=0.546fs. note 28 . the first stage of the interpolator . this is a passband gain amplitude of the 4 times oversampling filter. note 29 . the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/ 24 /32 bit data of both channels to the output of analog signal.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 16 - figure 3 . sharp roll - off filter frequency r esponse figure 4 . sharp roll - off filter passb and ripple
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 17 - slow roll - off filter characteristics slow roll - off filter characteristics (fs = 44.1 khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; normal speed mode; dem = off; sd bit or sd pin = 0, slow bit or slow pi n = 1 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency response ? ? ? ( note 26 ) sa 92 db group delay ( note 29 ) gd - 6.5 - 1/fs digital filter + scf ( note 26 ) frequency response: 0 ? slow roll - off filter characteristics (fs = 96khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; double speed mode; dem = off; sd bit or sd pin = 0, slow bit or slow pin = 1 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency responce ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? slow roll - off filter characteristics (fs = 192khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; quad speed mode; dem = off; sd bit or sd pin = 0, slow bit or slow pin = 1 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency responce ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? ? 0.01db), sb = 0. 8889 fs.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 18 - figure 5 . slow roll - off filter frequency response figure 6 . s low roll - off filter passband ripple
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 19 - short delay sharp roll - off filter characteristics short delay sharp roll - off filter characteristics (fs = 44.1 khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; normal speed mode; dem = off; sd bit or sd pin = 1, slow bit or slow pin = 0 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency responce ? ? ? di gital filter + scf ( note 26 ) frequency response: 0 ? short delay sharp roll - off filter characteristics (fs = 96khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; double speed mode; dem = off; sd bit or sd pin = 1, slow bit or slow pin = 0 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency responce ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? short delay sharp roll - off filter characteristics (fs = 192khz) (t a = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1 .7~1.98 v; quad speed mode; dem = off; sd bit or sd pin = 1, slow bit or slow pin = 0 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter freq uency responce ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? ? 0.01db), sb=0.546fs.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 20 - figure 7 . short d elay sharp roll - off filter frequency response figure 8 . short d elay sharp roll - off filter passband ripple
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 21 - short delay slow roll - off filter characteristics short delay slow roll - off filter characteristics (fs = 44.1 khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; normal speed mode; dem = off; sd bit or sd pin = 1 , slow bit or slow pin = 1 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency responce ? ? ? digit al filter + scf ( note 26 ) frequency response: 0 ? short delay slow roll - off filter characteristics (fs = 96khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dv dd = 1.7~1.98 v; double speed mode; dem = off; sd bit or sd pin = 1, slow bit or slow pin = 1 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency respon s e ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? short delay slow roll - off filter characteristics (fs = 192khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, av dd = tvdd = (dvdd) ? 3.6 v, dv dd = 1.7~1.98 v; quad speed mode; dem = off; sd bit or sd pin = 1, slow bit or slow pin = 1 , sslow bit or sslow pin = 0) parameter symbol m in . t yp . m ax . unit digital filter frequency respon s e ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? ? 0.01db), sb = 0. 8866 fs.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 22 - figure 9 . short d elay slow roll - off filter frequency response figure 10 . short d elay s low roll - off filter passband ripple
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 23 - low - dispersion s hort delay filter characteristics low - dispersion short delay filter characteristics (fs = 44.1 khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dv dd = 1.7~1.98 v; normal speed mode ; dem = off; sd bit pr sd pin = 1, slow bit or s low pin = 0 , sslow bit or sslow pin = 1) parameter symbol m in . t yp . m ax . unit digital filter frequency respon s e ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? low - dispersion short delay filter characteristics (fs = 96khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; double speed mode ; dem = off; sd bit pr sd pin = 1, slow bit or slow pin = 0 , sslow bit or sslow pin = 1) parameter symbol m in . t yp . m ax . unit digital filter frequency respon s e ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? low - dispersion short delay filter characteristics (fs = 1 9 2 khz) (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avd d = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; quad speed mode; dem = off; sd bit pr sd pin = 1, slow bit or slow pin = 0 , sslow bit or sslow pin = 1) parameter symbol m in . t yp . m ax . unit digital filter frequency respon s e ? ? ? digital filter + scf ( note 26 ) frequency response: 0 ? ? 0.0 5 db), sb = 0. 582 fs.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 24 - figure 11 . low d ispersion shortdelay filter frequency responce figure 12 . low d ispersion shortdelay filter passbandripple
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 25 - dsd filter characteristics (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = (dvdd) ? 3.6 v, dvdd = 1.7~1.98 v; fs = 44.1 khz; dp bit = 1, dsdsel[1:0] bits = 00) parameter m in . t yp . m ax . unit digital filter response ( note 34 ) dsdf bit = 0 1 01), and it is four times in 256 fs(dsdsel[1:0] bits = 10) . dc characteristics (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, avdd = tvdd = 1.7 ? 3.6 v , dvdd = 1.7~1.98 v ) parameter symbol m in . t yp . m ax . unit avdd= tvdd=1.7 ? ? ? ? ? ? ? ? ?
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 26 - switching characteristics (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, a vdd = t vdd = 1.7 ? 3.6v, dvdd = 1.7~1.98 v, c l = 20 pf ) parameter symbol min. typ. max. unit master clock timing frequency duty cycle minimum pulse width fclk dclk tclkh tclk l 2.048 40 9.155 9.155 - - - - 49.152 60 - - mhz % nsec nsec lrck clock timing ( note 37 ) normal mode (tdm[1:0] bits = 00) fsn fsd fsq fso fsh duty 8 54 108 - - 45 - - - 384 768 - 54 108 216 - - 55 khz khz khz khz khz % tdm128 mode (tdm[1:0] bits = 01) fsn fsd fsq tlrh tlrl 8 54 108 1/128fs 1/128fs - - - - - 54 108 216 - - khz khz khz nsec nsec tdm256 mode (tdm[1:0] bits = 10) fsn fsd tlrh tlrl 8 54 1/256fs 1/256fs - - - - 54 108 - - khz khz nsec nsec tdm 512 mode (tdm[1:0] bits = 11) fsn tlrh tlrl 8 1/512fs 1/512fs - - - 54 - - khz nsec nsec note 37 . the mclk frequency must be changed while the ak4492 is in reset state by setting the pdn p in = l or rstn bit = 0 .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 27 - (ta = - 40 ~ 85 ? c; vddl/r = 4.75 ? 5.25 v, tvdd = avdd = (dvdd) ? 3.6v , dvdd = 1.7~1.98 v, c l = 20 pf, psn pin = l , afsd bit = 1 ) parameter symbol min. typ. max. unit master clock timing (fs auto detect mode ) frequ ency duty cycle minimum pulse width fclk dclk tclkh tclkl 7.68 40 9.155 9.155 - - - - 49.152 60 - - mhz % nsec nsec lrck clock timing (fs auto detect mode ) ( note 38 ) normal mode (tdm[1:0] bits = 00) fsn fsd fsq fso fsh duty 30 88.2 176.4 - - 45 - - - 384 768 - 54 108 216 - - 55 khz khz khz khz khz % tdm128 mode (tdm[1:0] bits = 01) fsn fsd fsq tlrh tlrl 30 88.2 176.4 1/128fs 1/128fs - - - - - 54 108 216 - - khz khz khz nsec n sec tdm256 mode (tdm[1:0] bits = 10) fsn fsd tlrh tlrl 30 - 1/256fs 1/256fs - - - - 54 108 - - khz khz nsec nsec tdm512 mode (tdm[1:0] bits = 11) fsn tlrh tlrl 30 1/512fs 1/512fs - - - 54 - - khz nsec nsec note 38 . n ormal operation is not guaranteed if a frequency not shown above is input to the lrck when the ak449 2 is in sampling frequency auto detect mode .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 28 - parameter symbol m in . t yp . m ax . unit pcm audio interface timing normal mode (tdm[1:0] bits = 0 0) bick period normal speed mode double speed mode quad speed mode oct speed mode hex speed mode bick pulse width low bick pulse width high bick ? to lrck edge lrck edge to bick ? tbck tbck tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/256fsn 1/128fsd 1/64fsq 1/64fso 1/64fsh 9 9 5 5 5 5 - - - - - - - - - - - - - - - - - - - - - - nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec tdm128 mode (tdm[1:0] bits = 01) normal speed mode double speed mode quad speed mode bick pulse width low bick pulse width high bick ? to lrck edge dge to bick ? tdm256 mode (tdm[1:0] bits = 10) normal speed mode double speed mode ( note 40 ) bick pulse width low bick pulse width high bick ? to lrck edge lrck edge to bick ? tdmo setup time bick ? tdmo hold time bick ? tdm512 mode (tdm[1:0] bits = 11) normal speed mode ( note 41 ) bick pulse width low bick pulse width high bick ? to lrck edge lrck edge to bick ? tdmo setup time bick ? time bick ? tvdd < 3.0v . note 41 . daisy chain mode , fsn (max) = 48 khz if tvdd < 3.0v . note 42 . ldoe pin = l , tbsh (min) = 4 nsec if tvdd > 2.6v .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 29 - parameter symbol m in . t yp . m ax . unit pcm audio interface timing external digital filter mode bck period bck pulse width low bck pulse width high bck ? to wck edge wck edge to bck ? tb tbl tbh tbw twck twb twckl twckh tdh tds 27 10 10 5 1.3 5 54 54 5 5 - - - - - - - - - - - - - - - - - - - - nsec nsec nsec nsec usec nsec nsec nsec nsec nsec dsd audio interface timing sampling frequency fs 30 48 khz (64fs mode, dsdsel [1:0] bits = 00) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( not e 43 ) tdck tdckl tdckh tddd - 144 144 ? (128 fs mode, dsdsel [1:0] bits = 01) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( not e 43 ) tdck tdckl tdckh tddd - 72 72 ? (2 56fs mode, dsdsel [1:0] bits = 10) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( not e 43 ) tdck tdckl tdckh tddd - 36 36 ? . tddd is defined from dclk until dsdl/r edge when dckb bit = 0 (default), tddd is defined from dclk until dsdl/r edge when dckb bit = 1 . if the audio data format is in phase modulation mode, tddd is defined from dclk edge or until dsdl/r edge regardless of dck b bit setting.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 30 - parameter symbol m in . t yp . m ax . unit control interface timing (3 - wire if mode): cclk period cclk pulse width low cclk pulse width high cdti setup time cdti hold time csn h time ? to cclk ? cclk ? to ? control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prio r to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 44 ) sda setup time from scl rising rise time of both sda and scl lines fall time o f both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - - - - - - - - - - - - - - 400 - - - - - - - 0.3 0.3 - 50 400 khz usec usec usec usec usec usec usec usec usec usec nsec pf power - down & reset timing ( note 45 ) pdn accept pulse width pdn reject pulse width tapd trpd 150 - - - - 30 nsec nsec note 44 . data must be held for sufficient time to bridge the 300 ns transition time of scl. note 45 . the ak4 4 9 2 should be re set by bringing the pdn pin l upon power - up . note 46 . i 2 c - bus is a trademark of nxp b.v.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 31 - timing diagram figure 13 . c lock timing 1/fclk tclkl vih tclkh mclk vil dclk =tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tlrl tlrh tbck tbckl vih tbckh bick vil t wck t w ckl vih t w ckh w ck vil tb tbl vih tbh bck vil
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 32 - figure 14 . audio interface timing (pcm mode) figure 15 . audio interface timing (external digital filter i/f mode) tlrb lrck vih bick vil tdm o 5 0% t vdd tbss vih vil tblr tsds s d ata vih vil tsdh tbsh t wb w ck vih b ck vil t ds vih dinl dinr vil t dh vih vil tb w
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 33 - dsd audio interface timing (dsd64fs, 128fs, 256fs mode) figure 16 . audio interface timing (dsd phase modulation mode, dckb bit = 0) vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd vih dsdl dsdr vil vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd tddd vih dsdl dsdr vil tddd
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 34 - figure 17 . 3 wire serial mode write command input timing figure 18 . 3 wire serial mode write data input timing tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh tcck csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 35 - figure 19 . i 2 c bus m ode timing figure 20 . power down & reset timing thigh scl sda vih tlo w tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp tapd trpd pdn vil
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 36 - 9. functional descriptions each function of the ak449 2 is controlled by pins (pin control mode) and registers (register control mode) ( table 1 ) . select the control mode by setting the psn pin. the ak4492 must be powered down when changing the psn pin setting. there is a possibility of malfunction if the device is not powered down when changing the control mode since the previous s etting is not initialized. register settings are invalid in pin control mode, and pin settings are invalid in register control mode. table 2 shows available functions of each control mode and table 3 shows available functions in pcm/dsd/exdf mode. table 1 . pin/register control mode select psn pin control mode l register control mode h pin control mode table 2 . function list @pin/register control mode (y: available, - : not available) function pin control mode register control mode dsd/exdf mode select - y system clock setting select y y audio format select y y tdm mode y y digital filter select y y de - emphasis filt er select y y digital attenuator - y zero detection - y mono mode - y output signal select (monoral,channel select) - y output signal polarity select (invert) y y dsd full scale detect - y soft mute y y register reset - y clock synchronization fun ction - y resistor control - y gain control y y heavy load mode y y
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 37 - table 3 . function list of pcm/exdf/dsd m ode @register control mode (y: available, n/a: not available) function default addr bit pcm exdf dsd pcm/dsd/exdf mo de select pcm mode 00h 02h exdf dp y y y system clock setting @dsd mode 256fs 02h dcks - - y systemclock setting @ exdf mode 16fs (fs = 44.1 khz) 00h ecs - y - digital filter select @ dsd mode 39 khz filter 09h dsdf - - y digital filter select @ pcm mo de short delay sharp roll off filter 01 - 02 - 05h sd slow sslow y - - de - emphasis response off 01h dem[1:0] y - - path select @ dsd mode normal path 06h dsdd - - y audio data interface format @ pcm mode 32 bit msb 00h dif[2:0] y - - audio data interface format @ exdf mode 32 bit lsb 00h dif[2:0] - y - tdm interface format normal mode 0ah tdm[1:0] y - - daisy chain normal mode 0bh dchain y - - attenuation level 0 db 03 - 04h att[7:0] y y y data zero detect enable disable 01h dzfe y y y inverting enab le of dzf h active
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 38 - d/a conversion mode ( pcm m ode , dsd m ode , exdp m ode ) the ak4492 can perform d/a conversion for either pcm d ata or dsd data. when pcm mode, pcm data can be input from the bick, lrck and sdata pins. when dsd mode, dsd data can be input from the a3, b1 and b2 pins if dsdpath bit = 0 and dsd data can be input from the j1, h1, and g1 pins if dsdpath bit = 1 . th e dp bit controls pcm/dsd mode. the ak4492 must be reset by setting rstn bit = 0 when p c m/dsd mode is changed by dp bit or when dsd signal input pins are changed by dsdpath bit. it takes about 2 ~ 3/fs to change the mode. wait 4/fs or more to change rstn bit after changing these settings. external digital filter i/f can be selected by setting dp bit = 0 and exdf bit = 1 . when using an external digital filter (exdf i/f mode), data is input to each mclk, bck, wck, dinl and dinr pin. exd f bit controls the modes. when switching internal and external digital filters by exdf bit, the ak449 2 must be reset by rstn bit. a digital filter switching takes 2~3k/fs. the ak449 2 is in dsd mode when dp bit = 1 and exdf bit 1 . table 4 . pc m/dsd /exdf mode control dp bit exdf bit dsdpath bit d/a conv. mode pin assignment j1 pin h1 pin g1 pin a3 pin b1 pin b2 pin 0 (default) 0 (default) x pcm bick sdata lrck not use not use not use 1 x 0 (default) dsd not use not use not use d clk dsd l d sdr 1 x 1 dsd d clk dsd l d sdr not use not use not use 0 1 x exdf bck dinl dinr not use not use not use (x : do not c are ) d/a conversion mode switching timing figure 21 and figure 22 show switching timing of pcm/exdf and dsd modes . to prevent noise caused by excessive input, dsd signal shoul d be input 4/fs after setting rstn bit = 0 until the device is completely reset internally when the conversion mode is changed to dsd mode from pcm/esdf mode. dsd signal should be stopped 4/fs after setting rstn bit = 0 until the device is completely re set internally when the conversion mode is changed to pcm/exde from dsd mode. figure 21 . d/a mode switching timing ( from pcm or exdf to dsd) rstn bit d/a data d/a mode ? 4/fs ? 0 pcm or exdf data dsd data pcm or exdf mode dsd mode
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 39 - figure 22 . d/a mode switching timing ( from dsd to pcm or e xdf) figure 23 shows switching timing of pcm and exdf mode s. set exdf bit 4/fs after setting rstn bit = 0 until the device is completely reset internally when changing the conversion mode. figure 23 . d/a mode switching timing (pcm ? exdf) rstn bit d/a data d/a mode ? 4/fs dsd data pcm data dsd mode pcm or exdf mode ? 4 /fs rstn bit d/a data d/a mode ? 4/fs pcm or exdf data pcm or exdf data pcm or exdf mode pcm or exdf mode ? 4 /fs
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 40 - system clock [1] pcm m ode the external clocks, which are required to operate the ak449 2 , are mclk, bick and lrck. mclk , bick and lrck should be synchronize d but the phase is not critical. the mclk is used to operate t he digital interpolation filter , the delta-sigma modulator and scf . there are manual setting mode, auto setting mode and fs auto detection mode for mclk frequency setting ( table 5 ) . in manual setting mode (acks pin= l or acks bit= 0 ), m clk frequency is set automatically but the sampling speed (lrck frequency) is set by dfs[2:0] bits ( table 6 ). sampling frequency is fixed to normal speed mode in pin control mode (psn pin = h ), and it is set by d fs[2:0] bits in register control mode (psn pin = l ). in register control mode, the ak449 2 is in manual setting mode when power - down is released (pdn pin = l h ). in auto setti ng mode (acks pin = h or acks bit=1 ) , sampling speed and mclk fre quen cy are detected automatically ( table 7 , table 11 ) and the n the initial master clock is set t o the appropriate frequency ( table 8 , table 9 , table 15 , table 16 ). in fs auto detect mode ( afsd bit= 1 ) , sampling speed is automatically detected ( table 7 , table 11 ) a nd the initial master clock is set to the appropriate frequency. in this mode, acks bit and dfs[2:0] bits settings are invalid. fs auto detect mode is not supported by pin control mode . the ak449 2 is automatically pl aced in power - down state when mclk is stop ped for more than 1us during a normal operation (pdn pin = h ) , and the analog output becomes hi - z state . when mclk is input again, the ak4492 exit s power - down state a nd starts operation . the ak4492 is in power - down mode until mclk bick and lrck are supplied and the analog output is floating state. table 5 . system clock setting mode @register control mode afsd bit acks bit mode 0 0 manual set ting mode (default) 1 auto setting mode 1 x fs auto detect mode (x : do not c are )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 41 - (1) pin control mode (psn pin = h) ( 1 ) - 1 . manual setting mode (acks pin = l) the mclk frequency corresponding to each sampling speed should be provided externally ( table 6 ). dfs1 - 0 bi ts are f ixed to 00 . in this mode, quad sp eed and double speed modes a re not available. table 6 . system clock example (manual setting mode @pin control mode) lrck mcl k (mhz) bick fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs 64fs 32.0 khz n/a n/a 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 2.0480 mhz 44.1 khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a n/a 2.8224 mhz 48.0 khz n/a n/a 12.2880 18.4320 24.57 60 36.8640 n/a n/a 3.0720 mhz (n/a: not available) ( 1 ) - 2. auto setting mode (acks pin = h) in auto setting mode, mclk frequency and sampling frequency are detected automatically ( table 7 ) . mclk of correspond ed frequency to each sampling speed mode should be input externally ( table 8 , table 9 ) . table 7 . sampling speed (auto setting mode @pin control mode) mclk sampling speed 1152fs /1024fs normal (fs ?
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 42 - table 9 . system clock example 2 (aut o setting mode @pin control mode) lrck mclk (mhz) sampling speed fs 256fs 384fs 512fs 768fs 1024fs 1152fs 32.0 khz 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 normal 44.1 khz 11.2896 16.9344 22.5792 33.8688 n/a n/a 48.0 khz 12.2880 18.4320 24.5760 36.8640 n/a n/a 88.2 khz 22.5792 33.8688 n/a n/a n/a n/a double 96.0 khz 24.5760 36.8640 n/a n/a n/a n/a 176.4 khz n/a n/a n/a n/a n/a n/a quad 192.0 khz n/a n/a n/a n/a n/a n/a 384 khz n/a n/a n/a n/a n/a n/a oct 768 khz n/a n/a n/a n/a n/a n/a hex (n/a: not available) when mclk= 256fs/384fs, a uto s etting m ode supports sampling rate of 8 khz~96khz ( table 10 ). however , the dr and s/n performances will degrade approximately 3db as compared to when mclk = 2 56fs/384fs for dr and mclk= 512fs/768fs for s/n, respectively if the sampling rate is under 54khz. table 10 . dr and s/n relationship with mclk frequency (f s = 44.1khz) acks pin mclk dr, s/n l 256fs/384fs/512fs/768fs 12 3 db h 256f s/384fs 12 0 db h 512fs/768fs 12 3 db note 47 . this characteristic is supported by u sing external circuit ( figure 74 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 43 - (2) register control mode (psn pin = l) ( 2 ) - 1. manual setting mode (afsd bit = 0, acks bit = 0) mclk frequency is detected automatically and the sampling speed is set by dfs [2:0] bits ( table 11 ). the mclk frequency corresponding to each sampling speed that should be provided e xternally ( table 12 , table 13 ). the ak449 2 is set to manual setting mode at power - up (pdn pin = l h) . when dfs 2 - 0 bits are changed, the ak449 2 should be reset by rstn bit. table 11 . sampling speed (manual setting mode @register control mode) dfs2 bit dfs1 bit dfs0 bit sampling rate (fs) 0 0 0 normal speed mo de 8 khz ? ? ? ? 384 khz 1 1 1 hex speed mode 768 khz table 12 . system clock example 1 (manual setting mode @register control mode) lrck mclk (mhz) sampling speed fs 16fs 32fs 48fs 64fs 96fs 128fs 32.0 khz n/a n/a n/a n/a n/a n/a normal 44.1 khz n/a n/a n /a n/a n/a n/a 48.0 khz n/a n/a n/a n/a n/a n/a 88.2 khz n/a n/a n/a n/a n/a n/a double 96.0 khz n/a n/a n/a n/a n/a n/a 176.4 khz n/a n/a n/a n/a n/a 22.5792 quad 192.0 khz n/a n/a n/a n/a n/a 24.5760 384 khz n/a 12.288 18.432 24.576 36.864 n/a oct 768 khz 12.288 24.576 36.864 49.152 n/a n/a hex (n/a: not available) table 13 . system clock example 2 (manual setting mode @register control mode) lrck mclk (mhz) sampling speed fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs 32.0 khz n/a 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 normal 44.1 khz n/a 11.2896 16.9344 22.5792 33.8688 n/a n/a 48.0 khz n/a 12.2880 18.4320 24.5760 36.8640 n/a n/a 88.2 khz n/a 22.5792 33.8688 45.1584 n/a n/a n/a double 96.0 khz n/a 24.57 60 36.8640 49.152 0 n/a n/a n/a 176.4 khz 33.8688 45.1584 n/a n/a n/a n/a n/a quad 192.0 khz 36.8640 49.152 0 n/a n/a n/a n/a n/a 384 khz n/a n/a n/a n/a n/a n/a n/a oct 768 khz n/a n/a n/a n/a n/a n/a n/a hex (n/a: not available)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 44 - ( 2 ) - 2 . auto setting mode ( afsd bit= 0, acks bit = 1) mclk frequency and the sampling speed are detected automatically ( table 14 ) and dfs [2:0] bi ts are ignored. the mclk frequency corresponding to each sampling speed should be pr ovided externally ( table 15 , table 16 ). table 14 . sampling speed (auto setting mode) mclk sampling speed 1152fs /1024fs normal (fs ? characteristic is su pported by using external circuit ( figure 74 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 45 - ( 2 ) - 3. sampling frequency (fs) auto detect mode (afsd bi = 1) mclk frequency and the sampling rate is detected automatically ( table 14 ). in this mode, dfs[2:0] bits and acks bit settings are invalid. the mclk frequency corres ponding to each sampling speed should be provided externally ( table 18 , table 19 ). internal operation sequence in fs auto detect mode is shown in figure 24 . table 18 . system clock example 1 @pcm mode lrck mclk(mhz) sampling speed f s 16fs 32fs 48fs 64fs 96f s 128fs 32.0 khz n/a n/a n/a n/a n/a n/a normal 44.1 khz n/a n/a n/a n/a n/a n/a 48.0 khz n/a n/a n/a n/a n/a n/a 88.2 khz n/a n/a n/a n/a n/a n/a double 96.0 khz n/a n/a n/a n/a n/a n/a 176.4 khz n/a n/a n/a n/a n/a 22.5792 quad 192.0 khz n/a n /a n/a n/a n/a 24.5760 384 khz n/a 12.288 18.432 24.576 36.864 n/a oct 768 khz 12.288 24.576 36.864 49.152 n/a n/a hex (n/a: not available) table 19 . system clock example 2 @pcm mode lrck mclk (mhz) sampling speed fs 192fs 256 fs 384fs 512fs 768fs 1024fs 1152fs 32.0 khz n/a 8.1920 12.2880 16.3840 24.5760 32.768 36.8640 normal 44.1 khz n/a 11.2896 16.9344 22.5792 33.8688 n/a n/a 48.0 khz n/a 12.2880 18.4320 24.5760 36.8640 n/a n/a 88.2 khz n/a 22.5792 33.8688 45.1584 n/a n /a n/a double 96.0 khz n/a 24.5760 36.8640 49.152 0 n/a n/a n/a 176.4 khz 33.8688 45.1584 n/a n/a n/a n/a n/a quad 192.0 khz 36.8640 49.152 0 n/a n/a n/a n/a n/a 384 khz n/a n/a n/a n/a n/a n/a n/a oct 768 khz n/a n/a n/a n/a n/a n/a n/a hex (n/a: no t available)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 46 - ( 2 ) - 4 . power - down/up sequence in fs auto detect mode when using internal ldo. figure 24 . power - down/up s equence at fs autodetect mode note: (1) do not input a clock when power supplies are pow ered down. (2) the pdn pin must be held l for more than 150ns after turning on avdd , tvdd and vddl/r . (3) when the ldoe pin = h , the internal ldo starts ope ration after p ower up. the internal circuit will be powered up after the shutdown switch is on (max. 2ms ) following the internal oscillator count up. when the ldoe pin = l , the internal shutdown switch is on. the internal circuit will be powered up after the shutdown switch is on (max. 1ms). (4) when afsd bit = 1 , the internal oscillator starts operation . it takes 10 us (max) until the oscillation frequency is stabled. (5) after afsd bit = 1 , fs auto detect mode is started in 8/fs ~ 9/fs . (6) after afsd bit = 0 , the fs auto detect ciruit stop s internal operation and the osc is stopped. pdn pin power normal operation ( register write and dac operation are available ) clock in mclk, bick, lrck afsd bit internal osc internal fs auto detect circuit ( 4 ) ( 5 ) afsd bi t = 0 don t care internal state ( 2 ) i nternal pdn ( 3 ) dvdd pin f s auto dete ct mode enable afsd bit = 1 p ower up afsd bit = 0 (1 ) (6)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 47 - [ 2 ] dsd m ode th e ak4492 ha s a dsd playback function . the external clocks that are required in dsd mode are mclk and dclk . mclk should be synchronized with dclk but the phase is not critical . the frequency of mclk is set by dcks bit ( table 20 ). the ak449 2 is automatica lly placed in power - down state whe n mclk is stop ped during a normal operation (pdn pin = h ) , and the analog output become s hi - z state . when the reset is released (pdn pin = l h ), t he ak449 2 is in power - down state until mclk and dclk are input. table 20 . system clock (dsd mode , fs = 32 khz, 44.1 khz, 48 khz ) dcks bit mclk frequency dclk frequency 0 512fs 64fs/128fs/256fs (default) 1 768fs 64fs/128 fs/256fs the ak4492 supports dsd data stream of 2.82 24mhz (64fs), 5.6448mhz (128fs) and 11.2896mhz (256fs) . t he data sampling speed is selected by dsdsel [1:0] bits ( table 21 ) . table 21 . dsd d ata s tream s elect dsdsel1 dsdsel0 dsd data stream f s = 32 khz f s = 44.1 khz f s = 48 khz 0 0 2.048 mhz 2.8224 mhz 3.072 mhz (default) 0 1 4.096 mhz 5.6448 mhz 6.144 mhz 1 0 8.192 mhz 11.2896 mhz 12.288 mhz 1 1 n/a n/a n/a the ak4492 has a volume by pass function for play backing dsd signal. two modes are selectable by dsdd bit ( table 22 ) . when setting dsdd bit = 1 , the output volume cont rol and zero detect functions are not available. table 22 . dsd p lay b ack p ath s elect dsdd mode 0 normal path (default) 1 volume bypass
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 48 - [ 3 ] external digital f ilter mode (exdf m ode) the external clocks that are required in exdf mode are mclk , bck and wck . the bck a nd mclk clocks must be the same frequency and must not burst. bck and mclk frequencies for each sampling speed are shown in table 23 . ecs bit selects wck frequency from 384khz and 768khz. dw i n d icates the number of bck in one wck cyc le. all circuit s except the internal ldo are automatically placed in power - down state when mclk edge is not detected for more than 1us during a normal operation (pdn pin = h ), and the analog output becomes hi - z state . the power - down state is released and the ak449 2 starts operation by inputting mclk again. in this case, register settings are not initialized. when the reset is released (pdn pin = l h ), the ak4492 is in power - down state until mclk, bck and wck are input. table 23 . system clock example (exdf m ode) sampling speed[khz] mclk&bck [mhz] wck ecs 128fs 192fs 256fs 384fs 512fs 768fs 44.1(30~48) n/a n/a n/a n/a 22.5792 33.8688 16fs 0 (default) 32 48 dw 44.1(30~48) n/a n/a 11.2896 16.9344 n/a 33.8688 8fs 1 32 48 96 dw 96(54~96) n/a n/a 24.576 36.864 n/a n/a 8fs 0 32 48 dw 96(54~96) 12.288 18.432 n/a 36.864 n/a n/a 4fs 1 32 48 96 dw 192(108~192) 24.576 36.864 n/a n/a n/a n/a 4fs 0 32 48 dw 192(108~192) n/a 36.864 n/a n/a n/a n/a 2fs 1 96 dw
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 49 - audio interface format [1] pcm m ode (1) input data format data is shifted in via the sdata pin using bick and lrck inputs. eight d ata formats are supported and selected by the dif2 - 0 pins (pin control mode) or dif[2:0] bit s (register control mode) a s shown in table 24 . in all formats the serial data is msb first, 2's compliment format and is read on the rising edge of bick. mode 2 can be used for 20 - bit and 16 - bit msb justified form at s by zeroing the unused lsbs. normal mode ( tdm [1:0] bit s = 00 or t dm 1 - 0 pin s = ll ) 2ch data is shifted in via the sdata pin using bick and lrck inputs. eight d ata formats are supported and selected by the dif2 - 0 pins (pin control mode) or dif[2:0] b its (register control mode) as shown in table 24 . in all formats the serial data is msb first, 2's compliment format and is read on the rising edge of bic k. mode 6 can be used for 24 - bit, 20 - bit and 16 - bit msb just ified formats b y zeroing the unused lsbs. tdm128 mode ( tdm [1:0] bit s = 01 or tdm 1 - 0 pin s = lh ) 4ch data is shifted in via the sdata pin using bick and lrck inputs. data slot can be selected by sds[2:0] bits ( table 25 ). bick is fixed to 128fs. six d ata formats are supported and selected by the dif2 - 0 pins (pin control mode) or dif[2:0] bits (register control mode) as s hown in table 24 . in all formats the serial data is m sb first, 2's compliment format and is read on the rising edge of bick. tdm256 mode ( tdm [1:0] bit s = 10 or tdm 1 - 0 pin s = hl ) 8ch data is shifted in via the sdata pin using bick and lrck inputs. data slot can be selected by sds[2:0] bits ( table 25 ). bick is fixed to 256fs. six d ata formats are supported and selected by the dif2 - 0 pins (pin control mode) or dif[2:0] bits (register control mode) as shown in table 24 . in al l formats the serial data is msb first, 2's compliment format and is read on the rising edge of bick. tdm512 mode ( tdm [1:0] bit s = 11 or tdm 1 - 0 pin s = hh ) 16ch data is shifted in via the sdata pin using bick and lr ck inputs. data slot can be selected by sds[2:0] bits ( table 25 ). bick is fixed to 512fs. six d ata formats are supported and selected by the dif2 - 0 pins (pin control mode) or dif[2:0] bits (register control mode) as sh own in table 24 . in all formats the serial data is msb first, 2's compliment format and is read on the rising edge of bick.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 50 - table 24 . audio interface format mode tdm1 bit tdm0 bit dif2 bit dif1 bit dif0 bit sdata format lr ck bick figure normal ( note 49 ) 0 0 0 0 0 0 16 - bit lsb justified h/l ? 20 - bit lsb justified h/l ? 24 - bit msb justified h/l ? 16 - bit i 2 s compatible l/h 32fs figure 28 24 - bit i 2 s compatible l/h ? 24 - bit lsb justified h/l ? 32 - bit lsb justified h/l ? 32 - bit msb justified h/l ? 32 - bit i 2 s compatible l/h ? n/a - - - - - - - n/a - - - 8 0 1 0 24 - bit msb justified h/l 128fs figure 32 9 0 1 1 24 - bit i 2 s compatible l/h 128fs figure 33 10 1 0 0 24 - bit lsb justified h/l 128fs figure 34 11 1 0 1 32 - bit lsb justified h/l 1 28fs figure 32 12 1 1 0 32 - bit msb justified h/l 128fs figure 32 13 1 1 1 32 - bit i 2 s compatible l/h 128fs figure 33 td m256 - 1 0 - - - n/a - - - - - - - n/a - - - 14 0 1 0 24 - bit msb justified h/l 256fs figure 35 15 0 1 1 24 - bit i 2 s compatible l/h 256fs figure 36 16 1 0 0 24 - bit lsb justified h/l 256fs figure 37 17 1 0 1 32 - bit lsb justified h/l 256fs figure 35 18 1 1 0 32 - bit msb justified h/l 256fs figure 35 19 1 1 1 32 - bit i 2 s compatible l/h 256fs figure 36 tdm512 - 1 1 - - - n/a - - - - - - - n/a - - - 20 0 1 0 24 - bit msb justified h/l 512fs figure 38 21 0 1 1 24 - bit i 2 s compatible l/h 512fs figure 39 22 1 0 0 24 - bit lsb justified h/l 512fs figure 40 23 1 0 1 32 - bit lsb justified h/l 512fs figure 38 24 1 1 0 32 - bit msb justified h/l 512fs figure 38 25 1 1 1 32 - bit i 2 s compatible l/h 512fs figure 39 note 49 . bick more than setting bit must be input to each channel. in the lrck column, h/l indicates that l channel data can be input when lrck is h and r channel data can be input when lrck is l . l/h indicates l channel data can be input when lrck is l and r channel data can be input when lrck is h . note 50 . the default setting s in register control mode are show n below . tdm 1 bit = 0, tdm0 bit = 0, dif2 bit = 1, dif1 bit = 1, dif0 bit = 0
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 51 - figure 25 . mode 0 timing figure 26 . mode 1, 4 timing figure 27 . mode 2 timing sdata bick lrck sdata 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 (32fs) (64fs) 0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don t care don t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data sdata lrck bick (64fs) 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don t care don t care 19:msb, 0:lsb sdata mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don t care don t care 22 21 22 21 lch data rch data 8 23 23 8 lrck bick (64fs) sdata 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0 don t care 23 22 23
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 52 - figure 28 . mode 3 timing figure 29 . mode 5 timing figure 30 . mode 6 timing lrck bick (64fs) sdata 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don t care 23 lch data rch data 23 25 3 2 24 23 25 22 1 0 don t care 23 23 lrck bick(128fs) sdata 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1 0 31 1 bick(64fs) sdata 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31: msb, 0:lsb 8 0 1 8 0 1 lch data rch data 0 31 1 lrck bick(128fs) sdata 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 31 1 30 0 31 30 12 11 10 0 31 12 11 10 bick(64fs) sdata 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31: msb, 0:lsb 8 0 1 8 0 1 lch data rch data
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 53 - figure 31 . mode 7 timing figure 32 . mode 8/11/12 timing figure 33 . mode 9/13 timing lrck bick(128fs) sdata 0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1 31 0 31 13 12 11 0 13 12 11 bick(64fs) sdata 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 0 1 31 9 0 31 21 20 19 9 0 21 20 19 31: msb, 0:lsb 8 1 2 8 1 2 lch data rch data lrck bick(128fs) 128 bick l1 32 bick r1 32 bick 3 2 bick 32 bick sd ata 22 0 22 0 23 23 22 23 mode 8 sd ata 30 0 30 0 31 31 30 31 mode 11 ,1 2 lrck bick(128fs) 128 bick l1 32 bick r1 32 bick 32 bick 32 bick sd ata 22 0 22 0 23 23 23 sd ata mode 9 mode1 3 30 0 30 0 31 31 30 31
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 54 - figure 34 . mode 10 timing figure 35 . mode 14/17/18 timing figure 36 . mode 15/19 timing figure 37 . mode 16 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick 32 bick 32 bick sd ata 22 0 22 0 23 23 23 23 lrck bick (256fs) 22 0 l1 32 bick 256 bick 22 0 r1 32 bick 22 23 23 32 bick 32 bick s d ata 31 30 0 30 31 31 30 0 s data mode 14 mode 17 ,1 8 32 bick 32 bick 32 bick 32 bick lrck bick (256fs) 23 0 l1 32 bick 256 bick 23 0 r1 32 bick 23 32 bick 32 bick sd ata mode 15 31 0 31 30 31 0 30 sd ata mode1 9 32 bick 32 bick 32 bick 32 bick lrck bic k(256fs) sd ata 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 32 bick 32 bick 23 23 23 32 bick 32 bick 32 bick 32 bick
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 55 - figure 38 . mode 20/23/24 timing figure 39 . mode 21/25 timing figure 40 . mode 22 timing bick(512fs) s data mode8 lrck 512bick 22 2 0 23 22 0 23 s data mode11,12 l1 32 bick r1 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 22 0 31 23 22 0 31 31 bick(512fs) s data mode 21 lrck 512bick 22 2 0 23 22 0 23 s data mode 25 l1 32 bick r1 3 2 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 22 0 31 23 22 0 31 31 bick(512fs) s data mode 22 lrck 512bick 22 2 0 23 22 0 23 l1 32 bick r1 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 3 2 bick 32 bick 32 bick 32 bick 32 bick 32 bick 23
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 56 - (2) data slot selection function data slot of 1cycle lrck for each audio data format is defined as figure 41 ~ figure 44 . dac output data can be select ed by sds[2:0] bits as shown in table 26 . figure 41 . data slot in normal mode figure 42 . data slot in tdm12 8 mode figure 43 . data slot in tdm256 mode figure 44 . data slot in tdm512 mode lrck sd ata r1 l1 sd ata r1 l1 lrck 128 bick r 2 l2 sd ata r1 l1 lrck 256 bick r 2 l2 r 3 l 3 r 4 l 4 sd ata r1 l1 lrck 512 bick r 2 l 2 r 3 l 3 r 4 l 4 r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 57 - table 25 . output data slot select ion of eac h channel tdm1 tdm0 sds2 sds1 sds0 dac lch rch normal 0 0 x x x l1 r1 tdm128 0 1 x x 0 l1 r1 x x 1 l2 r2 tdm256 1 0 x 0 0 l1 r1 x 0 1 l2 r2 x 1 0 l3 r3 x 1 1 l4 r4 tdm512 1 1 0 0 0 l1 r1 0 0 1 l2 r2 0 1 0 l3 r3 0 1 1 l4 r4 1 0 0 l5 r5 1 0 1 l6 r6 1 1 0 l7 r7 1 1 1 l8 r8 ( x : do not care )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 58 - ( 3 ) daisy chain the ak 4492 supports cascading of multiple devices by daisy chain connection in tdm 512/ 256 mode ( tdm[1:0] bits = 10, 11 ) . dchain bit or dchain pin controls daisy chain mode ( table 26 ). sds[2:0] bits setting will be invalid in daisy chain mode. table 26 . daisy chain control dchain bit dchain pin mode tdmo pin 0 normal l (default) 1 daisy chain data output ( 3 ) - 1. tdm512 m ode figure 45 shows daisy chain connection in tdm512 mode (tdm[1:0] bits = 11) . 16ch data is input to th e sdata pin of the second ak4492 and the tdmo pin of the second ak449 2 is connected to the sdata pin of the first ak449 2. figure 46 shows data input/output example of daisy chain in tdm512 mode. the second ak4492 receives l8 and r8 data as dac inputs and outputs the data by s hifting 2ch from the tdmo pin. th e first ak4492 receives l7 and r7 data as dac input. settings of dif[2:0] bits of the first and second ak4492 s must be the same. figure 45 . daisy chain (tdm512 mode) figure 46 . daisy chain (tdm512 mode) first ak44 9 2 second ak44 9 2 dsp s d ata tdmo sd ata tdmo sd ata r1 l1 lrck 512 bick r 2 l 2 r 3 l 3 r 4 l 4 r 5 r 6 l 6 r 7 l 7 r 8 l 8 l 5 tdmo r 2 r 3 l 3 r 4 l 4 r 5 l 5 l 2 second ak44 9 2 first ak44 9 2 r 1 l 1 r 6 l 6 r 7 l 7 l 8 r 8
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 59 - (3) - 2. tdm256 m ode figure 45 shows daisy chain connection in tdm 256 mode (tdm[1:0] bits = 1 0 ) . 8ch data is input to the sd ata pin of the second ak449 2 and the tdmo pin of the second ak449 2 is connected to t he sdata pin of the first ak4492 . figure 47 shows data input/output example of daisy chain in tdm256 mode. the second ak449 2 rece ives l4 and r4 data as dac inputs and outputs the data from the tdmo pin b y shifting 2ch. the first ak4492 receives l3 and r3 data as dac input. settings of dif[2:0] bits of the first and second ak449 2 s must be the same. figure 47 . daisy chain (tdm256 mode) [2] dsd m ode in dsd mode, l channel data and r channel data must be input to the dsdl pin and the dsdr pin, respectively by synchronizing to dclk. input pins can be selected by dsdpath bit. when dsd path bit = 0 , the tdm0 pin, the dem pin and the gain pin become dclk, dsdl and dsdr input pins, respectively. when dsdpath bit = 1 , the bick pin , the sdata pin and the lrck pin become dclk , dsdl and dsdr input pins, respectively. in case of dsd mode, the settings of dif2 - 0 pins and dif[2: 0 ] bits are ignored. the frequency of dclk is selected between 64fs, 128fs and 25 6fs by dsdsel[1:0] bits. polarity of dclk is possible to reverse at dckb bit. figure 48 . dsd mode timing sdata r1 l1 lrck 256 bick r 2 l2 r3 l3 r 4 l4 tdmo r1 l1 r 2 l2 second ak4 49 2 first ak44 9 2 r3 l3 r 4 l4 dclk ( 64fs, 128 fs ,256fs ) dckb bit = 1 dclk ( 64fs, 128 fs ,256fs ) dckb bit = 0 dsdl,dsdr normal dsdl,dsdr phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 6 0 - [3] external digital filter mode (exdf m ode) the audio data is input by bck and wck from the dinl and dinr pins . three formats are available ( table 27 ) by dif2 - 0 bits setting. the data is latched on the rising edge of bck. the bck and mclk clocks must not burst. table 27 . audio interface format (exdf m ode) mode dif2 dif1 dif0 input format 0 0 0 0 16 - bit lsb justified 1 0 0 1 n/a 2 0 1 0 16 - bit lsb justified 3 0 1 1 n/a 4 1 0 0 24 - bit lsb justified 5 1 0 1 32 - bit lsb justified 6 1 1 0 24 - bit lsb justified (default) 7 1 1 1 32 - bit lsb justified (n/a: not available) figure 49 . exdf mode timing bck w ck dinl or dinr 23 22 bck 0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1 21 20 17 16 0 5 1 6 7 8 47 48 49 65 92 93 94 95 0 1 31 30 3 1 0 15 14 6 5 4 3 2 1 0 don t care don t care dinl or dinr 2 31 24 don t care don t care bck 0 1 3 1 14 15 16 23 24 25 44 45 46 47 0 1 3 1 0 don t care dinl or dinr 2 31 don t care don t care 1/16fs or 1/8fs or 1/4fs o r 1/2fs
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 61 - digital filter six types of digital filter in pcm mode and two types of digital filter in dsd mode are available in the ak449 2 for sound color selection of music playback. in pcm mode, digital filter can be selected by the sd, slow and sslow pins if th e ak4492 is in pin control mode, and digital filter can be selected by sd, slow and sslow bits in register control mode ( table 28 ). table 28 . digital filter setting sslow sd slow mode 0 0 0 sharp roll - off filter 0 0 1 slow roll - off filter 0 1 0 short delay sharp roll - off filter (default) 0 1 1 short delay slow roll - off filter 1 0 0 super slow roll - off filter 1 0 1 super slow roll - off filter 1 1 0 low dispersion shot delay filter ) 1 1 1 n/a note 51 . do not use reserved mode (sslow bit= 1 , sd bit= 1 , slow bit= 1 ) in pcm mode. in dsd mode, the cutoff frequency of digital filter can be switched by dsdf bit . table 29 shows the cutoff frequency of fs = 44.1 khz. the cutoff frequency tracks the sampling frequency (fs). do not set g c [2:0] bits to 100 when dsdd bit = 0 and dsdf bit = 1 . otherwise a pop noise may occur. table 29 . dsd f ilter s elect dsdf bit cut off frequency @fs=44.1khz, dsd64fs dsd128fs dsd256fs 0 39 khz 78 khz 156 khz (default) 1 76 khz 152 khz 304 khz
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 62 - de - emphasis f i lter (pcm mode ) a digital de-emphasis filter is available for 32 khz , 44.1 khz or 48 khz sampling rates (tc = 50/15s) and is enabled or disabl ed by dem1 - 0 pins or dem 1 - 0 bits . when dsd mode or exdf mode, dem1 - 0 bits are ignored. the setting value is held even if pcm, dsd and exdf mode is switched. table 30 . de - emp hasis control dem1 dem0 mode 0 0 44.1 khz 0 1 off (default) 1 0 48 khz 1 1 32 khz output volume (pcm mode , dsd mode , exdf mode ) the ak449 2 includes channel independent digital output volumes ( att l/r ) wit h 256 levels at 0.5db step including mute. when changing output levels, it is executed in soft transition thus no switching noise o ccurs during these transitions . it can attenuate the input data from 0db to - 127db and mute when assuming the output signal level is 0db when attl/r[7:0] bits = ffh . table 31 . attenuation level of digital attenuator attl/r[7:0]bi ts (register 03 - 04h) attenuation level ffh +0 db (default) feh - 0.5 db fdh - 1.0 db : : 02h - 126.5 db 01h - 127.0 db 00h mute ( - 0, 0 1 0 1 ffh (0db) to 00h (mute) in mode 0 . the attenuation level is initialized to ffh (0db) by setting the pdn pin = l . if the volume is changed during reset period, the output volume will become a setting value after releasing the reset. it will change to a setting va lue immediately if the volume is changed within 5/fs after releasing reset.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 63 - gain adjustment function (pcm mode , dsd mode , exdf mode ) the ak449 2 has the gain adjustment function. the analog output amplitude can be adjusted by gc[2:0] bits or the gain pin. table 33 . output level between set values of gc [2:0] bit s gc[2] bit gc[1] bit gc[0] bit aoutlp/ln/rp/rn ou t put level pcm dsd: normal path dsd: volume bypass 0 0 0 2.8 vpp 2.8 vpp 2.5 vpp (default) 0 0 1 2.8 vpp 2.5 vpp 2.5 vpp 0 1 0 2.5 vpp 2.5 vpp 2.5 vpp 0 1 1 2.5 vpp 2.5 vpp 2.5 vpp 1 0 0 3.75 vpp 3.75 vpp 2.5 vpp 1 0 1 3.75 vpp 2.5 vpp 2.5 vpp 1 1 0 2.5 vpp 2.5 vpp 2.5 vpp 1 1 1 2.5 vpp 2.5 vpp 2.5 vpp table 34 . output level between se t values of gain pin ( valid only in pcm mode ) gain pin aoutlp/ln/r p/rn ou t put level l 2.8 v pp h 3.75 vpp note 52 . dsdf bit must be set to 0 if gc[2:0] bits are set to 100 when using dsd normal path . click noise may occur if dsdf bit is se t to 1 .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 64 - zero detection (pcm mode , dsd mode , ex df mode ) the ak449 2 has a channel - independent zero detect function. when the input data at each channel is continuously zero s for 8192 lrck cycles, the dzf pin of each channel outputs zero detection flag independently . polarity of the detection flag of th e dzfl/r pin can be selected by dzfb bit. the dzfl/r pin goes h for zero detection when dzfb bit = 0 , the dzfl/r pin goes l when dzfb bit = 1 . when dzfb bit = 0 , the dzf l/r pin immediately returns to l if the input data of each channel is no t zero after going to h . if the rstn bit is 0 , the dzf pins of both l and r channels go to h . the dzf l/r pin returns to l in 4 ~ 5/fs after the input data of each channel becomes 1 when rstn bit is set to 1 . if dzfm bit is set to 1 while dzf b bit = 0 , the dzf pins of both l and r channels go to h only when the input data for both channels are continuously zeros for 8192 lrck cycles. the z ero detect function can be disabled by setting the dzfe bit. in this case, dzf pins of both channels a re always l . the zero detect function is also disabled when volume bypass is selected in dsd mode ( table 22 ). table 35 . zero d etect s elect. dzfe dzfb rstn data dzf pin 0 0 - - l 1 - - h 1 0 0 - h 1 not zero l zero detect h 1 0 - l 1 not zero h zero detect l ( - : do not care)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 65 - l / r channel output s i gnal select, phase inversion functio n (pcm mode , dsd mode , exdf mode ) in register control mode, input and output combination of the ak449 2 can be changed by mono bit and sellr bit. in addition, the output signal phase can be inverte d by invl bit and invr bit. these functions are available on all audio formats. in pin control mode, the phase of r channel output can be inverted by setting the invr pin. table 36 . output select (register control) mono bit sellr bit invl bit invr bit lch out rch out 0 0 0 0 lch in rch in 0 1 lch in rch in invert 1 0 lch in invert rch in 1 1 lch in invert rch in invert 0 1 0 0 rch in lch in 0 1 rch in lch in invert 1 0 rch in invert lch in 1 1 rch in invert lch in invert 1 0 0 0 lch in lch in 0 1 lch in lch in invert 1 0 lch in invert lch in 1 1 lch in invert lch in invert 1 1 0 0 rch in rch in 0 1 rch in rch in invert 1 0 rch in invert rch in 1 1 rch in invert rch in invert table 37 . output select (pin control) invr pin lch out rch out 0 lch in rch in 1 lch in rch in invert
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 66 - dsd signal full scale (fs) detection the ak449 2 has independent full scale detection function for each channel in dsd mode. the ak449 2 detects full scale signal when the dsdl/r input data is continuously 0 ( - fs) or 1 (+fs) for 2048 cycles and the de tection flag for corresponding channel (dml or dmr bit) becomes 1 . dml and dmr bits can be read out at the register address 06h . when the ak449 2 detects full scale signal while ddm bit = 1 , the analog output is muted according to table 38 . ats[2:0] bits control a mute transition time. ats[2:0] bits and dsdd bit settings are also valid when the ak449 2 returns to normal status from full scale detection status. the recovery timing from full scale detection st atus and the operation mode of full scale detection are controlled by ddm bit, dmc bit and dmre bit. rstn bit must be set to 0 when changing ddm bit setting. table 38 . dsd mode and device status after full - scale detection (ddm b it= 1) dsdd mode analog output mute transition method 0 normal path vcml/r (mute) soft mute (default) 1 volume bypass vcml/r (mute) rapid mute table 39 . recovery m ethod to n ormal o peration m ode from f ull s cale d etection s tat us d dm dm c dmre status after detection 0 x x when full scale is detected, mute function is disabled. (default) 1 0 x when full scale is detected, mute function is enabled. t he ak449 2 returns to normal operation automatically by a normal signal input. 1 1 0 when full scale is detected, mute function is enabled. t he ak449 2 keeps mute mode, even if a normal signal is input. 1 1 1 ( note 53 ) when full scale is detected, mute function is enabled. t he ak449 2 returns to normal operation when a normal signal is input and dmre bit is set to 1 0 automatically after the ak449 2 returns to normal operation .
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 67 - figure 50 . analog output waveform in dsd fs detection (dmc bit= 0) figure 51 . analog output waveform in dsd fs detection (dmc bit= 1) dsd error (d ml or d mr bit) dsd data dsd data dsd data (fs or - fs ) dsd data 2048fs aout (dsdd bit= 1 ) aout (dsdd bit= 0 ) att transition period att transition period dsd error (dml or dmrbit) dsd data dsd data dsd data (fs or - fs ) dsd data 2048fs aout (dsdd bit= 1 ) aout (dsdd bit= 0 ) dmre bit att transition period att transition period
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 68 - soft mute operation (pcm mode , dsd mode , exdf mode ) the soft mute operateion is performed at digital domain. when the smute pin goes to h or the smute bit set to 1 , the output signal is attenuated by ? ? during att_data ? att transition ( 1 setting per 16/fs ) time from the current att level . when the smute pin is returned to l or the smute bit is returned to 0 , the mute is cancelled and the output attenuation gradually changes to the att level during att_data ? att transition time( refer to table 32 for att ) . if the soft mute is cancelled before attenuating ? ? after starting the operation, the attenuation is discontinued and returned to att level by the same cycle . the soft mute is effective for changing the signal source without stopping the signal transmission. figure 52 . soft mute function note: (1) att_data ? att transition ti me. for example, this time is 4080lrck cycles at att_data=255 in pcm normal spee d mode. (2) the a nalog outpu t corresponding to the digital input has group delay (gd). (3) if the soft mute is cancelled before attenuating ? ? after starting the operation, the attenuation is discontinued and returned to att level by the same cycle . (4) when the input data for each channel is continuously zeros for 8192 lrck cycles, the dzf pin for each channel goes to h . the dzf pin immedia tely returns to l if the input data is not zero. smute pin or smute bit attenuation dzf l/r pin att_level - ? aout l/r 8192/fs gd gd (1) (2) (3) (4) (1) (2)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 69 - ldo when tvdd = 3.0 ~ 3.6v , the power for digital core circuit (dvdd) is supplied by the internal ldo by setting the ldoe pin to h . table 40 shows the dvdd pin statuses with the pdn and ldoe pins setting. the internal ldo is powered up by setting the pdn pin from l to h (power - do wn release) and it starts supping 1.8v dvdd. it takes 0.1ms (max.) to power - up the internal ldo. table 40 . ldo s elect m ode pdn pin ldoe pin tvdd dvdd x l 1.7~3.6 v ldo off: supply 1.7 ~ 1.98v to the dvdd pin externally l h 3.0~3. 6 v 500 ohm pull down h h 3.0~3.6 v ldo on: ldo outputs 1.8v . (do not connect dvdd with other devices.) (x: do not care ) the ak4492 has error detect function as shown in table 41 for ldo operation (ldoe pin = h) . the internal ldo will be powered down and stop supplying the power to the digital core when an error is detected. in this case, the analog signal output become s unstable . the ak449 2 must be reset by setting the pdn pin = l h to recover from the error detection status. table 41 . error detection no error error detection condition 1 internal reference voltage error internal reference voltage does not rise. 2 ldo over voltage detection threshold is from 2.2v to 2.5v. 3 ldo ove r current detection ldo current is 40ma or less, or 110ma or more. shutdown switch a shutdown switch is placed between the dvss pin and vss for the digital core to prevent sidd leak of dvdd digital power supply. the o n - resistance is maximum 1 and the dvdd leak current will be 2ua at the maximum. when using ldo (ldoe pin = h ), the shutdown switch is on after counting by internal oscillator following a power - down release (pdn pin l h ). it takes 2ms (max.) for the shutdown switch power - up. when not using ldo (ldoe pin = l ), the shutdown switch is on immediately after a power - down release (pdn pin l h ). it takes 1us (max.) for the shutdown switch power - up.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 70 - power up/down function the ak449 2 is powered down by setting the pdn pin to l . in power - down state, all circuits stop operation and initialized, and the analog output becomes floating (hi - z) state. the pdn pin must held l for more than 1 50n s for a certain reset. the re is a possibility of malfunc tions with the l pulse less than 1 50ns. power - down is released by setting the pdn pin to h from l . in this time iref and ldo (if ldoe pin = h ) are powered up and the analog output becomes floating (hi - z) state. the analog common voltage power up af ter by pdn pin to h . the time to be stable voltage is in propotional to the capacitance of the vcml pin and the vcmr pin. for example, when the capacitance is 1uf, the time constant is about 3ms. (1 ) pin control mode (psn pin = h ) all circuits will be powered up by inputting mclk, lrck and bick clocks after the pdn pin = h . the analog circuit starts operation just after supplying all necessary clocks (mclk, lrck and bick) and the digital circuit starts operation about 4/fs after the clock supply. figure 53 shows system timing example of power down/up when using the internal ldo (ldoe pin h ). when power up the ak4492 with the ldoe pin = h , 3.3v power supplies (avdd and tvdd) should be powered up before or a t the same time of 5v power s upplies (vddl/r). figure 53 . power - down/up s equence e xample (pincontrol mode, ldoe pin = h ) notes : (1) do not input a clock when power supplies are powered down. (2) the pdn pin m ust be held l for more than 150ns after avdd , tvdd and vddl/r reached 90%. (3) internal ldo is powered up after the pdn pin = h when the ldoe pin= h . the internal circuit will starts operation after the shutdown switch is on (max. 2ms) following the int ernal oscillator count up. (4) the a nalog outpu t corresponding to the digital input has group delay (gd). (5) analog outputs are floating (hi - z) in power down mode. (6) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. pdn pin power ( vddl / r) reset normal operation (dac input available) clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on ( 7 ) 0 data gd ( 4 ) ( 6 ) gd ( 6 ) mute on 0 data internal state ( 5 ) ( 5 ) ( 2 ) i nternal pdn ( 3 ) d vdd pin power ( tvdd,avdd ) analog reference ( v refhl , vrefhr) don t care ( 8 ) ( 1 ) ( 1 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 71 - (7) mute the analog output externally if click noise ( 6 ) adversely affect system performance . (8) clock inputs (mclk, bick and lrck) can be stopped in power down state. the timing example when not using the internal ldo (lode pin = l ) is shown in figure 54 . when the ldoe pin= l , 1.8v (dvdd) , 3.3v (avdd, tvdd) and 5v (vddl, vddr) power supplies should be powered up at the same time, otherwise power up 3.3v power suppl ies (avdd, tvdd) first, the 1.8v power supply (dvdd) nex t and 5v power supplies ( vddl/r ) last. figure 54 . power - down/up s equence e xample (pin control mode, ldoe pin= l ) notes : (1) do not input a clock when power supplies are powered down. (2) the pdn pin must be he ld l for more than 150ns after avdd , tvdd , dvdd and vddl/r reached 90%. (3) internal shutdown switch is powered up after the pdn pin = h when the ldoe pin= l . the internal circuit will start operation after the shutdown switch is on (max. 1us). (4) the a nal og outpu t corresponding to the digital input has group delay (gd). (5) analog outputs are floating (hi - z) in power down mode. (6) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (7) mute the analog output externally if cli ck noise ( 6 ) adversely affect system performance . (8) clock inputs (mclk, bick and lrck) can be stopped in power down state. power ( d vdd ) reset normal operation (dac input available) clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on ( 7 ) 0 data gd ( 4 ) ( 6 ) gd ( 6 ) mute on 0 data internal state ( 5 ) ( 5 ) i nternal pdn ( 3 ) power ( tvdd,avdd ) power ( v ddl/r ) don t care ( 8 ) ( 1 ) analog reference ( v refhl/r) pdn pin ( 2 ) ( 1 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 72 - (2 ) register control mode (psn pin= l ) a register access becomes available after the pdn pin = h . the analog circuit starts opera tion by supplying necessary clocks (mclk, lrck and bick for pcm mode, mclk and dclk for dsd mode, mclk, bck and wck for exdf mode) and the clock divider is powered up about after 4/fs. the analog output pins output analog common voltages (vcml, vcmr) in th is time. then the ak449 2 transitions to normal operation by setting rstn bit = 1 . when power up the ak449 2 with the ldoe pin = h , 3.3v power supplies (avdd and tvdd) should be powered up before or at the same time of 5v power supplies (vddl/r). figure 55 . power - down/up s equence e xample (resister control mode, ldoe pin= h ) notes : (1) do not input a clock when power supplies are powered down. (2) the pdn pin must be held l for more than 150ns after avdd , tvd d and vddl/r reached 90%. (3) internal ldo is powered up after the pdn pin = h when the ldoe pin= h . the internal circuit will starts operation after the shutdown switch is on (max. 2ms) following the internal oscillator count up. (4) the a nalog outpu t corre sponding to the digital input has group delay (gd). (5) analog outputs are floating (hi - z) in power down mode. (6) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (7) mute the analog output externally if click noise ( 6 ) ad versely affect system performance . (8) the dzf l/r pin is l in power - down mode (pdn pin = l). (9) the clock divider is powered up in about 4/fs after the internal pdn is released. (10) it takes 3~4/fs until a reset instruction is valid when writing rst n bit to 0 and it takes 2~3/fs when releasing the reset. (11) clock inputs (mclk, bick and lrck) can be stopped in power down state. pdn pin analog reference (vrefhl/r) clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mut e on ( 9 ) 0 data gd ( 6 ) gd mute on 0 data internal state (digital core) ( 5 ) ( 5 ) ( 2 ) i nternal pdn ( 3 ) d vdd pin power ( tvdd,avdd ) dzfl/r ( 8 ) rstn bit normal operation normal operation ( 6 ) internal state (resister (clock devider) power off ( 4 ) ( 9 ) ( 10 ) ( 10 ) ( 1 ) ( 1) (1 1 ) power (vddl/r) power off power off power off don t care
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 73 - the system timing example of power up/down when not using ldo (lode pin = l ) is shown in figure 56 . when the ldoe pin= l , 1.8v (dvdd) , 3.3v (avdd, tvdd) and 5v ( vddl, vddr) power supplies should be powered up at the same time, otherwise power up the 3.3v power suppl ies (a vdd, tvdd) first, 1.8v power supply (dvdd) next and 5v power supplies ( vddl/ r ) last. figure 56 . power - down/up s equence e xample (resister control mode, ldoe pin = l ) notes : (1) do not input a clock when power supplies are powered down. (2) the pdn pin must be held l for more than 150 ns after avdd , tvdd and vddl/r reached 90%. (3) internal shutdown switch is powered up after the pdn pin = h when the ldoe pin= l . the internal circuit will start operation after the shutdown switch is on (max. 1us). (4) the a nalog outpu t corresponding to the digital input has group delay (gd). (5) analog outputs are floating (hi - z) in power down mode. (6) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (7) mute the analog output externally if click noise ( 6 ) adversely affect system perf ormance . (8) the dzf l/r pin is l in power - down mode (pdn pin = l). (9) the clock divider is powered up in about 4/fs after the internal pdn is released. (10) it takes 3~4/fs until the internal rstn is changed when changing rstn bit to 0 and it takes 2~ 3/fs when changing rstn bit to 1 . (11) clock inputs (mclk, bick and lrck) can be stopped in power down state. pdn pin analog reference (vrefhl/r) clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on ( 7 ) 0 data gd ( 6 ) gd mute on 0 data internal state (digital cor e) ( 5 ) ( 5 ) ( 2 ) i nternal pdn ( 3 ) power ( tvdd,avdd ) dzfl/r ( 8 ) rstn bit normal operation normal operation ( 6 ) internal state (resister (clock devider) power off ( 4 ) ( 9 ) ( 10 ) ( 10 ) ( 1 ) ( 1) ( 11 ) power (vddl/r) power off power off power off don t care power (d vdd )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 74 - power - off/reset function power - off and reset function of the ak449 2 are controlled by pw bit, rstn bit and mclk ( table 42 ). table 42 . power o ff , reset f unction mode pdn pin mclk supply pw bit rstn bit digital block analog block ldo register analog output power down l [ 1 ] power on/off by mclk clock the ak449 2 detects a clock stop and all circuits including mclk stop detection circu it, control register and iref (except ldo when the ldoe pin = h ) stop operation if mclk is not input for 1us (min.) during operation (pdn pin = h ). in this case, the analog output goes floating state (hi - z). the ak4492 returns to normal operation if pw bit and rstn bit are 1 after starting to supply mclk again. the zero detect function is disabled when mclk is stopped. figure 57 . power on/off by mclk clock notes: (1) the ak4492 detects mclk stop and becomes power off state whe n mclk edge is not detected for 1us (min.) during operation . (2) the analog output goes to floating state (hi - z). (3) click noise can be reduced by inputting 0 data when stopping and resuming mclk supply. (4) resume mclk input to release the power - off state by mcl k . in this case, power - up sequence by the pdn pin or power - on sequence by pw b it is n ot necessary. (5) the a nalog outpu t corresponding to the digital input has group delay (gd). normal operation internal state power - off normal operation d/a out (analog) d/a in (digital) clock in mclk, ( 1 ) mclk stop pdn pin (1) (2) hi - z ( 4 ) (3 ) (5)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 75 - [ 2 ] power on/off by pw bit all circuits including control register and iref (ex cept ldo when the ldoe pin = h ) stop operation by setting pw bit to 0 . in this case, control register access is available. the analog output goes to floating state (hi - z). figure 58 shows power on/off sequence by pw bit. figure 58 . power on/off timing example notes : (1) the a nalog outpu t corresponding to the digital input has group delay (gd). (2) the analog output is floating (hi - z) state when pw bit = 0 . (3) click noise occurs at the edge of pw bit . this noise is output even if 0 data is input. (4) the zero detect function is enable when the ak449 2 is power off (pw bit= 0) . this figure shows the seuqnece when dzfe bit= 1 , dzfb bit = 0 and dzfm bit= 0 . (5) it takes 4~5/fs until a power down instruction is valid when writing pw bit and it takes 1~2/fs when releasing the power down. ( 6 ) mute the analog output externally if click noise ( 3 ) or hi - z output (2) adversely affect system performance . internal state pw bit p ower - off normal operation gd gd 0 data da c out ( analog) da c in (digital) (1) (3) (3) (1) (2) hi - z normal operation rstn bit ( 4 ) dzfl/dzfr external mute ( 6 ) mute on ( 5 ) ( 5 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 76 - [ 3 ] reset by rstn bit digital circuits except control register s and clock divider are reset by setting rstn bit to 0 . in this case, contro l register settings are held, the analog output becomes vcml /r voltage and the dzfl/r pin output s h . figure 59 shows power on/off sequence by rstn bit. figure 59 . reset timing example notes (1) the a nalog outpu t corresponding to the digital input has group delay (gd). (2) the analog output is vcom voltage when rstn bit = 0 . (3) click noise occurs at the edge of pw bit . this noise is output even if 0 data is input. (4) this figure shows the seuqnece when dzfe bit= 1 , dzfb bit = 0 and dzfm bit= 0 . the dzfl/r pin goes h on a falling edge of rstn bit and goes l 2/fs after a rising edge of internal rstn bit. (5) it takes 3~4/fs until the internal rstn is changed when changing rstn bit to 0 and it takes 2~3/fs when changing rstn bit to 1 . (6) mute the analog output externally if click noise ( 3 ) advers ely affect system performance . internal state rstn bit digital block p ower - off normal operation gd gd 0 data d a c out (analog) d a c in (digital) (1) (3 ) dzf l/r (3) (1) (2) normal operation 2/fs(4) internal rstn signal 2~3/fs (5) 3~4/fs (5) (6)
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 77 - synchronize function (pcm m ode , exdf m ode ) the ak449 2 has a function that resets the inter nal counter to keep the timing of falling edge of the internal clock clk1 and the external clock edge in a certain range. w i th this synchronize function, group del ays between each device can be kept within 4/256fs when using multiple ak449 2 s. clock synchronize function becomes valid when input data of both l and r channels are 0 for 8192 times continuously in pcm mode or exdf mode, when both l and r channels bec ome 0 and kept for 8192 times continuously by attenuation or when rstn bit = 0 . in pcm mode, the internal counter is synchronized with a rising edged of lrck (falling edge of lrck in i2c mode), and it is synchronized with a rising edge of wck in exdf m ode. in this case, the analog output has the same voltage as vcml/r. this function is disabled by setting synce bit = 0 in register control mode. figure 60 shows a synchronizing sequence when the input data is 0 for 8192 times continuously. figure 61 shows a synchronizing sequence by rstn bit. figure 60 . synchronizing sequenc by c ontinuous 0 d ata input for 8192 t i mes notes : (1) regarding att transition time, refer to output volume (pcm mode , dsd mode , exdf mode ) . (2) when both l and r channels data are 0 fo r 8192 times continuously, the dzfl and dzf r pins become h a nd the synchronize function is valid. (3) internal data is fixed to 0 forcibly for 2 to 3 /fs when internal counter is reset. (4) a click noise may occur when the internal counter is reset. this noise is output even if a 0 data is input. mute the analog output externally if this click noise affects the system performance. (5) when the internal clock and external clock are in synchronization, the internal counter is not reset even if the synchronize function is valid. smute attenuation b oth dzf l/r pin att_level - ? aout 8192/fs gd (1) (2 ) (1) d/a in (digital) gd gd 8192/fs (2 ) sync operation ( 2 ) sync operation ( 2 ) internal counter reset internal data 2~3/fs ( 3 ) ( 4 ) (5 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 78 - if rstn bit is set to 0 , the outp ut signal of the dzfl/ r pin becomes h . then, the dac is reset after 3~ 4/fs and the analog output becomes the same voltage as vcml/r. the synchronize function becomes valid when both of the dzfl and the dzfr pins output h . figure 61 . synchronizing sequence by rstn b it notes : (1) the dzfl and the dzf r pin s becom e h by a falling edge of rstn bit, and becomes l 2/fs after a rising edge of internal signal of rstn bit. the synchronize function is v alid during the dzfl/r pin = h . (2) internal data is fixed to 0 forcibly for 2 to 3 /fs when the internal counter is reset. (3) since t he analog output corresponding to digital input has group delay (gd) , it is recommended to have a no - input period long er than the group delay before writing 0 to rstn bit. (4) it takes 3 to 4/fs when falling to change the internal rstn signal of the lsi after writing to rstn bit. it also takes 2 to 3 /fs when rising to change the internal rstn signal of the lsi. the sync hronize function becomes valid immediately when 0 is written to rstn bit. therefore, there is a case that the internal counter is reset before internal rstn signal of the lsi is changed. (5) a click noise occurs on the rising or falling edge of the inte rnal rstn signal and when the internal counter is reset. this noise is output even if a 0 data is input. mute the analog output externally if this click noise affects the system performance. internal state rstn bit digital block power - down normal operation gd gd d/a out (analog) d/a in (digital) ( 3 ) ( 5 ) both dzf l/r pin ( 5 ) ( 3 ) normal operation 2/fs(4) internal rstn bit 2~3/ fs (4 ) 3 ~4/fs (4 ) internal counter r eset internal data 2~3/fs ( 2 ) force 0 sync operation (1) ( 2 )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 79 - register control interface [ 1 ] 3 - wire serial control mode (i2c pin = l) pins (p in control mode) or registers ( register control mode) can control the functions of the ak449 2 . in p in control mode, the register setting is ignored, and in register contro l mode the pin settings are ignored. when the state of the psn pin is changed, the ak449 2 should be powered down by the pdn pin. otherwise, malfunction s may occur since previous settings are not initialized. the register control interface is enabled by the psn pin = l. internal registers may be written to through 3 - wire p interface pins: csn, cclk and cdti. the data on this interface consists of chip address (2 - bits, c 1/0 ), read/write (1 - bit; fixed to 1 , write only ), register address (msb first, 5 - bits ) and control data (msb first, 8 - bits). the data is output on a falling edge of cclk and the data is received on a rising edge of cclk. the writing of data is valid when csn ? . the clock speed of cclk is 5mhz (max) . setting the pdn pin to l resets the registers to their default values. in register control mode, the digital block except control registers and clock divider is reset by setting rstn bit to 0 . in this case, the register values are not initialized. c1 - c0: chip address (c1 bit = cad1 pin, c0 bit = cad0 pin) r/w: read/write (fixed to 1, write only) a4 - a0: register address d7 - d0: control data figure 62 . control i/f timing * the ak449 2 does not support read command s in 3 - wire serial c ontrol mode . * when the ak449 2 is in power down mode (pdn pin = l) , writing into control register s is prohibited. * the control data can not be written when the cclk rising edge is 15 times or less , or 17 times or more during csn is l. * the cdti pin mu st not fall during the cclk pin is h . w riting into registers may not be valid when it is happened . cdti cclk c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 80 - [ 2 ] i 2 c - bus control mode (i2c pin = h) the ak4 4 9 2 supports the fast - mode i 2 c - bus (max: 400khz , ver . 1.0 ). (1) write operations figure 63 shows the data transfer sequence for the i 2 c - bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 69 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as 00100. the next bit s are cad 1 and cad0 (device address bit s ). this bit identifies the specific device on the bus. the hard - wired input pin ( cad1 pin, cad0 pin) sets these device address bits ( figure 64 ). if the slave address matches that of t he ak4 4 9 2 , the ak4 4 9 2 generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 70 ). a r/w bit value of 1 indicates that the read operation is to be executed, and 0 indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4 4 9 2 and t he format is msb first . ( figure 65 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 66 ). the ak4 49 2 generates an acknowledge after each byte is received. data tra nsfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 69 ). the ak4 4 9 2 can perform more than one byte wr ite operation per sequence. after receipt of the third byte the ak4 4 9 2 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after rece iving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 15h prio r to generating a stop condition, the address counter will roll over to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only be changed when the clock signal on the scl line is low ( figure 71 ) except for the start and stop conditions. figure 63 . data transfer sequence at i 2 c bus mode 0 0 1 0 0 cad1 cad0 r/w figure 64 . the first byte 0 0 0 a4 a3 a2 a1 a0 figure 65 . the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 66 . the third byte and after the third byte sda s t a r t a c k a c k s slave address a c k sub address(n) data(n) p s t o p data( n+x) a c k data(n+1) a c k r/w= 0 a c k
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 81 - (2) read operation set the r/w bit = 1 for the read operation of the ak449 2 . after transmi ssion of data, the master can read the next addresss data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. after receiving each data packet the internal address counter is incremented by one, an d the next data is automatically taken into the next address. if the address exceeds 15h prior to generating stop condition, the address counter will roll over to 00h and the data of 00h will be read out. the ak449 2 supports two basic read operati ons: c urrent a ddress r ead and r andom a ddress r ead . (2) - 1. c urrent a ddress r ead the ak449 2 has an internal address counter that maintains the address of the last accessed word incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit 1, the ak449 2 generates an acknowledge, transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak449 2 ceases the transmission. figure 67 . c urrent address re ad (2) - 2 . r andom a ddress r ead the random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit 1 , the master must first perform a dummy write operation. the master issues a star t request, a slave address (r/w b it = 0) an d then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit 1 . the ak449 2 then generates an acknowl edge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak449 2 ceases the transmission. figure 68 . random address read sda s t a r t a c k a c k s slave address a c k data(n+1) p s t o p data( n+x) a c k data(n+2) a c k r/w= 1 a c k data(n) sda s t a r t a c k a c k s slave address a c k data(n) p s t o p data( n+x) a c k data(n+1) a c k r/w= 0 a c k sub address(n) s t a r t a c k s slave address r/w= 1
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 82 - figure 69 . start condition and stop condition figure 70 . acknowledge (i 2 c bus) figure 71 . bit transfer (i 2 c bus) scl sda stop condition start condition s p scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 scl sda data line stable; data valid change of data allowed
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 83 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks exdf ecs afsd dif2 dif1 dif0 rstn 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smute 02h control 3 dp 0 dcks dckb mono dzfb sellr slow 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 05h control4 invl invr 0 0 0 0 dfs2 sslow 06h dsd1 ddm dml dmr dmc dmre 0 dsdd dsdsel0 07h control5 0 0 0 0 gc2 gc1 gc0 synce 08h sound control 0 0 0 0 hload 0 0 0 09h dsd2 0 0 0 0 0 dsdpath dsdf dsdsel1 0ah control 7 tdm1 tdm0 sds1 sds2 0 pw 0 0 0bh control 8 ats1 ats0 0 sds0 0 0 dchain 0 0ch reserved 0 0 0 0 0 0 0 0 0dh reserved 0 0 0 0 0 0 0 0 0eh reserved 0 0 0 0 0 0 0 0 0fh reserved 0 0 0 0 0 0 0 0 10h reserved 0 0 0 0 0 0 0 0 11h reserved 0 0 0 0 0 0 0 0 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 0 0 0 0 0 14h reserved 0 0 0 0 0 0 0 0 15h dfs read 0 0 0 0 0 adfs2 adfs1 adfs0 notes: ? in 3 - wire serial c ontrol mode, the ak4492 does not suppor t read commands. ? the ak4492 supports read command in i 2 c - bus c ontrol m ode . ? if the address exceeds 15h , the address counter will roll over to 00h and the next write/read address will be 00h by automatic increment function in i 2 c - bus mode. ? bits indicated as 0 in each address must contain a 0 value . writing after 16h is also forbidden . malf unctions may occur by these action s . ? when the pdn pin goes to l, the registers are initialized to their default values. ? when rstn bit is set to 0, t he digital block except control registers and clock divider is reset, and the registers are not initialized to their default values. ? when the state of the psn pin is changed, the ak449 2 shou ld be reset by the pdn pin.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 84 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks exdf ecs afsd dif2 dif1 dif0 rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 1 0 0 rstn: internal timing reset 0: reset. all registers are not initial ized. (default) 1: normal operation dif[2:0]: audio interface format ( table 24 ) initial value is 110 (mode6: 32bit msb justified ). afsd: sampling frequency auto detect mode enable (pcm & exdf mode only) . ( table 5 ) 0: disable: manual or auto setting mode (default) 1: enable: auto detect mode when afsd bit = 1, dfs[2:0] bits are ignored. ecs: exdf mode clock setting ( table 23 ) 0: wck = 768khz mode(default) 1: wck = 384khz mode exdf: external digital filter i/f mode (register control mode only) 0: disable: internal digital filter mode (default) 1: enable: external digital filter mode acks: master clock frequency auto setting mode enable (pcm & exdf mode only) ( table 14 , table 5 ) 0: disable: manual setting mode (default) 1: enable: auto setting mode
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 85 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smute r/w r/w r/w r/w r /w r/w r/w r/w r/w default 0 0 1 0 0 0 1 0 smute: soft mute enable 0: normal operation (default) 1: dac outputs soft - muted. dem[1:0]: de - emphasis control ( table 30 ) initial value is 01 (off). dfs[1:0 ]: sampling speed control. ( table 7 , table 11 ) initial value is 000 (normal speed). click noise occurs when dfs[2:0] bits are changed. sd: minimum delay filter enable. ( table 28 ) 0: traditional filter 1: short delay filter (default) dzfm: data zero detect mode 0: channel separated mode (default) 1: channel anded mode if the dzfm bit is set to 1, the dzf pins of both l and r channels go to h only when the input data at both channels are continuously zeros for 8192 lrck cycles. dzfe: data zero detect enable 0: disable (default) 1: enable zero detect function can be disabled by dzfe bit 0. in this ca se, the dzf pins of both channels are always l.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 86 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 dp 0 dcks dckb mono dzfb sellr slow r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 slow: slow roll - off filter enable. ( table 28 ) 0: slow roll - off filter disable (default) 1: slow roll - off filter sellr: the data selection of l channel and r channel, when mono mode 0: all channel output l channel data, when mono mode. (default ) l channel output l channel data, r channel data output r channel data(default) 1: all channel output r channel data, when mono mode. l channel output r channel data, r channel data output l channel data dzfb: inverting enable of dzf . ( table 35 ) 0: dzf pin goes h at zero detection (default) 1: dzf pin goes l at zero detection mono: mono mode stereo mode select 0: stereo mode (default) 1: mono mode dckb: polarity of dclk (dsd only ) 0: dsd data is output from dclk falling edge. (default) 1: dsd data is output from dclk rising edge. dcks: master clock frequency select at dsd mode (dsd only) 0: 512fs (default) 1: 768fs dp: dsd/pcm mode select 0: pcm mode (default) 1: dsd mod e when dp bit is changed, the ak4492 should be reset by rstn bit.
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 87 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 1 1 1 1 1 1 1 1 att[7:0]: attenuation level 255 levels 0.5 db step + mute data attenuation ffh 0 db (default) feh - 0.5 db fdh - 1.0 db : : : : 02h - 126.5 db 01h - 127.0 db 00h mute ( - ? ) addr register name d7 d6 d5 d4 d 3 d2 d1 d0 05h control 4 invl invr 0 0 0 0 dfs2 sslow r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ssl ow: super slow roll off (digital filter bypass mode) enable. ( table 28 ) 0: disable (default) 1: enable d fs2: sampling speed control. ( table 7 , table 11 ) invr: aoutr output phase inverting 0: disable (default) 1: enable invl: aoutl output phase inverting 0: di sable (default) 1: enable
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 88 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dsd1 ddm dml dmr dmc dmre 0 dsdd dsdsel0 r/w r/w r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dsdsel[1:0]: dsd data stream select table 21 . dsd d ata s tream s elect dsdsel1 dsdsel0 dsd d ata s tream f s = 32 khz fs = 44.1 khz f s = 48 khz 0 0 2.048 mhz 2.8224 mhz 3.072 mhz (default) 0 1 4.096 mhz 5.6448 mhz 6.144 mhz 1 0 8.192 mhz 11.2896 mhz 12.288 mhz 1 1 n/a n/a n/a dsdd : dsd p layback p ath select table 22 . dsd play b ack path select d sdd mode 0 normal path (default) 1 v o lume bypass dmre: dsd m ute r elease 0: hold (default) 1: release mute this register is only valid when ddm bit = 1 and dmc bit = 1 . whe n the ak449 2 mutes dsd data by ddm and dmc bits settings, the mute is released by setting dmre bit to 1 . table 39 . recovery m ethod to n ormal o peration m ode from f ull s cale d etection s tatus d dm dm c dmre status after detection 0 x x when full scale is detected, mute function is disabled. (default) 1 0 x when full scale is detected, mute function is enabled. t he ak449 2 returns to normal operation automatically by a normal signal input. 1 1 0 when full scale is detected, mute function is enabled. t he ak449 2 keeps mute mode, even if a normal signal is input. 1 1 1 ( note 53 ) when full scale is detected, mute function is enabled. t he ak449 2 returns to normal operation when a normal signal is input and dmre bit is set to 1 0 automatically after the ak449 2 returns to normal operation . dmc: dsd m ute c ontrol 0: auto return (default) 1: mute hold (manual return) this register is only valid when ddm bit = 1 . it selects the mute releasing mode of when the dsd data level becomes under full - scale after the ak449 2 mutes dsd data by ddm bit setting. dmr/dml this register outputs detection flag when a full scale signal is detected at dsdr/l channel. ddm: dsd d ata m ute the ak449 2 has an internal mute function that mutes the output when dsd audio data becomes all 1 or all 0 for 2048 s ample s ( dclk cycle). ddm bit controls this function. 0: disable (default) 1: enable
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 89 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h control 5 0 0 0 0 gc2 gc1 gc0 synce r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 synce: sync mode enable 0: sync mode disable 1: sync mode enable (default) gc[2:0]: pcm, dsd m ode gain control table 33 . output level between set values of gc [2:0] bit gc[2] bit gc[1] bit gc[0] bit aoutlp/ln/rp/rn ouput level pcm dsd: normal path dsd: volume bypass 0 0 0 2.8 vpp 2.8 vpp 2.5 vpp (default) 0 0 1 2.8 vpp 2.5 vpp 2.5 vpp 0 1 0 2.5 vpp 2.5 vpp 2.5 vpp 0 1 1 2.5 vpp 2.5 vpp 2.5 vpp 1 0 0 3.75 vpp 3.75 vpp 2.5 vpp 1 0 1 3.75 vpp 2.5 vpp 2.5 vpp 1 1 0 2.5 vpp 2.5 vpp 2.5 vpp 1 1 1 2.5 vpp 2.5 vpp 2.5 vpp addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h sound control 0 0 0 0 hload 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 hload: heavy load mode enable 0: heavy load mode disable (default) 1: heavy load mode enable
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 90 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h dsd2 0 0 0 0 0 dsdpath dsdf dsdsel1 r/w r r r r r r/w r/w r/w default 0 0 0 0 0 0 0 0 dsdsel [ 1 :0] : dsd data stream select table 21 . dsd data stream select dsdsel1 dsdsel0 dsd data stream f s = 32 khz f s = 44.1 khz f s = 48 khz 0 0 2.048 mhz 2.8224 mhz 3.072 mhz ( default) 0 1 4.096 mhz 5.6448 mhz 6.144 mhz 1 0 8.192 mhz 11.2896 mhz 12.288 mhz 1 1 n/a n/a n/a dsdf: cut - off frequency of dsd filter c ontrol table 29 . dsd f ilter s elect dsdf bit cut off frequency @fs = 44.1 khz, ds d64fs dsd128fs dsd256fs 0 39 khz 78 khz 156 khz (default) 1 76 khz 152 khz 304 khz dsdpath: dsd d ata i nput p in s elect 0: a3 , b1 , b2 (default) 1: j 1, h 1, g 1 table 4 . pc m/dsd /exdf mode control dp bit exdf bit dsdpath bit d/a conv. mode pin assignment j1 pin h1 pin g1 pin a3 pin b1 pin b2 pin 0 (default) 0 (default) x pcm bick sdata lrck not use not use not use 1 x 0 (default) dsd not use not use not use d clk dsd l d sdr 1 x 1 dsd d clk dsd l d sdr not use no t use not use 0 1 x exdf bck dinl dinr not use not use not use (x : do not c are )
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 91 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah control 7 tdm1 tdm0 sds1 sds2 0 pw 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 1 0 0 pw: power on/off co ntrol 0 : power off 1 : power on (default) sds[ 2 :0]: output data slot selection of each channel ( table 25 ) table 25 . output data slot select ion of eac h channel tdm1 tdm0 sds2 sds1 sds0 d ac lch rch normal 0 0 x x x l1 r1 tdm128 0 1 x x 0 l1 r1 x x 1 l2 r2 tdm256 1 0 x 0 0 l1 r1 x 0 1 l2 r2 x 1 0 l3 r3 x 1 1 l4 r4 tdm512 1 1 0 0 0 l1 r1 0 0 1 l2 r2 0 1 0 l3 r3 0 1 1 l4 r4 1 0 0 l5 r5 1 0 1 l6 r 6 1 1 0 l7 r7 1 1 1 l8 r8 (x : do not care) tdm[1:0]: tdm mode select 00: normal (default) 01: tdm128 10: tdm256 11: tdm512
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 92 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh control 8 ats1 ats0 0 sds0 0 0 dchain 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dchain: daisy chain mode enable 0: daisy chain mode disable (default) 1: daisy chain mode enable sds[ 2 :0]: output data slot selection of each channel 0: normal operation 1: changing data slot ( table 25 ) default value is 00 . ats[1:0]: transition time between set values of att[7:0] bits ( table 32 ) default value is 00 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch reserved 0 0 0 0 0 0 0 0 0dh reserved 0 0 0 0 0 0 0 0 0eh reserved 0 0 0 0 0 0 0 0 0fh reserved 0 0 0 0 0 0 0 0 10h reserved 0 0 0 0 0 0 0 0 11h reserved 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0ch : reserved 0dh : reserved 0 e h : reserved 0 f h : reserved 10 h : reserved 11 h : reserved
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 93 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 0 0 0 0 0 14h reserved 0 0 0 0 0 0 0 0 r/w r r r r r r r r default 0 0 0 0 0 0 0 0 12h : reserved 13h : reserved 14h : reserved addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h adfs read 0 0 0 0 0 adfs2 adfs1 adfs0 r/w r r r r r r r r default 0 0 0 0 0 0 0 0 adfs[2:0] : mode detection result in fs auto detect mode table 43 . jugdement result of mode and adfs[2:0] adfs2 bit adfs1 bit adfs0 bit mode 0 0 0 normal speed mode 0 0 1 double speed mode 0 1 0 quad speed mode 0 1 1 quad speed mode 1 0 0 oct speed mode 1 0 1 hex speed mode 1 1 0 oct speed mode 1 1 1 hex speed mode
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 94 - 10. recommended external circuits figure 72 . typical connection diagram (avdd = tvdd = dvdd = 1.8 v, vddl/r = 5.0 v, ldoe pin = l, register control mode) note : - chip address = 00. bick = 64f s, lrck = fs - power lines of avdd , tvdd, vdd l and vddr should be distributed separately from the point with low impedance of regulator etc. - avss, dvs s, vssl and vssr must be connected to the same analog ground plane. (analog ground should has low impe dance as a solid pattern. thd+n characteristics will degrade if there are impedances between each vss. ) - it is recommended to input mclk via a dumping resistor of 51ohm. without the resistor, there is a possibilrty that thd+n characteristic degrades beca use of high - frequency noise of mclk. - all input pins except pull-down/pull - up pins should not be allowed to float. b ick/bck/dclk(j1 ) acpu d vss 0v s data/dinl/dsdl(h1 ) lrck/dinr/dsdr( g1 ) s low/cdti/sda(e1 ) d if0/dzfl(d1 ) d if1/dzfr(c1 ) d em0/dsdl(b1 ) d vss(k2 ) t vdd(j2 ) p dn(h2 ) s slow/wck (g2 ) t dmo(f2 ) dvdd 1.8v s d/cclk/scl(e2 ) d if2/cad0(d2 ) h load/i2c(c2 ) gain/dsdr(b 2 ) a cks/cad1(a2 ) d vdd(k3 ) l doe(h 3 ) p sn(d3) t dm1(b3 ) t dm0/ dclk(a3 ) a vdd(k4 ) a vss(j4 ) d chain(b4 ) i nvr(a4 ) vss dvss a k4492 s mute/csn(f1 ) 0.1 ? f 0.1 ? f 0.1 ? f mclk( j3 ) 1 ? f 51ohm e xtr(j5 ) 33kohm vss 0v t este(b5 ) a outr p(b 9) a outrn(a9 ) external lpf circuit aoutr v ssr(d10,e9,e10 ) v ddr(c9 , c10 , d9 ) 1 ? f vrefhl( k5 , k6 ) v refll(l7,k8 ) external regulator circuit v cml(j8 ) 1 ? f aoutln( k9 ) aoutlp(j 9 ) external lpf circuit aoutl v ddl(g9,h9,h10 ) v ssl(f9,f10,g10 ) 1 ? f v cmr(b8 ) vreflr( a7,a8 ) external regulator circuit v refhr(a5 , a6 ) 1 ? f vdd 5v power supply 6v
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 95 - 1. grounding and power supply decoupling to minimize coupling by digital noise, decoupling capacitors should be co nnected to avdd , tvdd, dvdd, vddl and vddr . avdd and vddl/r are supplied from analog supply in system , and t vdd and dvdd are supplied from digital s upply in system. power lines of vddl/r should be distributed separately from the point with low impedance of regulator etc. when n ot using the ldo (ldoe pin = l), all power supplies (dvdd (1.8v), tvdd and avdd (3.3v) and vddl/r (5v)) should be powered up at the same time or sequentially in the order of 3.3v (tvdd, avdd), 1.8v (dvdd) and 5v (vddl/r). the internal ldo outputs dvdd (1.8v) when the ldoe pin = h. 3.3v (tvdd and avdd) power supplies must be powered up before or at the same time with 5v (vddl/r) power supplies when the ldoe pin = h. avss, dvss, vssl and vss r mus t be connected to the same analog ground plane. decoupli ng capacitors for high frequency should be placed as near as possible to the supply pin. 2. voltage reference the differential voltage between vrefhl/r and vrefll/ r sets the full scale of the analog output range. the vrefhl/r pin is normally connected t o vdd , and the vrefll/r pin is normally connected to the vss . the vrefh, vrefl pin should be connected to the noiseless power supply. if not, it is recommended to connect these pin to an external regulator circuit as shown in figure 73 . in this case, a tantalum or an electrolytic capacitor ( 6.8u ) should be used between each of the vrefhl and vrefhr pins, and the vrefll and vreflr pin s. digital sign al and clock lines should be kept away from the vrefhl/r and vrefll/r pins in order to avoid u nwanted coupling into the ak4 492 . low noise 5v (typ.) should be input to the external regulator circuit. if this input voltage has a noise, attenuate the noise by a 1st order lpf as shown in figure 73 . no load current may be drawn from the vcml/r pin since vc m l/r is a common voltage of analog signals. figure 73 . external regulator circuit example 3. analog output the analog outputs a re full differential output s. t he differential outputs are summed externally, v aout = (aout+) ? (aout ? ) between aout+ and aout ? . if the summing gain is 1, the output range of the setting the gain pin = l or gc[2] bit = 0 is 2.8 vpp (typ , vref hl/r ? vref ll/r = 5v) centered around vcml and vcmr voltages . in this case, the output range after summing will be 5.6v (typ.). the output range of the setting the gain pin = h or gc[2] bit = 1 is 3.75vpp (typ.) centered around vcml and vcmr voltages. in this cas e, the output range after summing will be 7.5vpp (typ.). the bias voltage of the external summing circuit is supplied externally. the input data format is 2's complement. the output voltage (v aout ) is a positive full scale for 7fffffffh (@32bit) and a neg ative full scale for 80000000h (@32bit) . the ideal v aout is 0v for 00000000h (@32bit) . the internal switched-capacitor filter s attenuate the noise generated by the delta-sigma modulator beyond rlp +vop + 5v v refhr pin opa1611 6 2 3 4 7 clp v refl r pin rlp +vop v refhl pin opa1611 6 2 3 4 7 clp v refll pin 1st order lpf 6.8u 6.8u
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 96 - the audio passband. figure 74 show s example s of external lpf circuit summing the differential outputs by a single op - amp. l oad resistances of the analog output of the ak4492 are 1360 ohm for aout+ and 453 ohm for aout - , and t he external lpf circuit can be driven regardless of the hload pin or hload bit setting. the hload pin/bit should be set to h/1 when driving the lpf circuit if the aout - load resistance is 300 ~ 400 ohm. the analog output will be 5.6 vpp (typ.) after a single conversion with this circuit by setting the gai n pin = l or gc[2] bit = 0 . it w ill be 7.5 vpp if setting the gain pin = h or gc[2] bit = 1 . a resistor that has 0.1% or less absolute error must be used for external lpfs. figure 74 . external lpf circuit example 1 (fc = 90 khz(typ), q = 0.705(typ)) table 43 . frequency response of external lpf circuit example 1 gain(1 khz,typ) 0 db frequency response (ref:1 khz,typ) 20 khz - 0.04 db 40 khz - 0.22 db 80 khz - 2.08 db 680 68 0 3 0 68 0 3 0 68 0 +vop 3.3 n - vop aout - aout+ analog out 3.3 n ak449 2 opa1611 6 2 3 4 7 22 n
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 97 - 4 . connectio n example with the ak81 57 a the ak8157a is the multi clock generater for the audio product with low rms gitter. mclk, bclk and lrck are generated by the ak8157a. connection example of the ak4492 and the external device is as follows. e.g . a k 8157 : master / external dsp : slave mclk, bclk and lrck are generated by the ak8157a. sdata for the ak449 2 is output from the external dsp in synchronization with bclk and lrck. system rayout should be designed so that a noise interference between vss and dvss does not occure . figure 75 . circuit example with ak8157a d vss 0v dvdd 1.8v vss dvss 0.1 ? f 51ohm a k8157 9.6mhz dsp micro - controller bick sdata lrck mcl k cl k in bick lrck mcl k sda scl rstn b ick/bck/dclk(j1 ) s data/dinl/dsdl(h1 ) lrck/dinr/dsdr( g1 ) s low/cdti/sda(e1 ) d vss(k2 ) t vdd(j2 ) d if2/cad0(d2 ) h load/i2c(c2 ) a cks/cad1(a2 ) d vdd(k3 ) l doe(h 3 ) p sn(d3) t dm1(b3 ) a vdd(k4 ) a vss(j4 ) d chain(b4 ) i nvr(a4 ) a k4492 s mute/csn(f1 ) mclk( j3 ) t este(b5 ) a outrp(b 9) a outrn(a9 ) v ssr(d10,e9,e10 ) v ddr(c9 , c10 , d9 ) vrefhl( k5 , k6 ) v refll(l7,k8 ) v cml(j8 ) aoutln( k9 ) aoutlp(j 9 ) v ddl(g9,h9,h10 ) v ssl(f9,f10,g10 ) v cmr(b8 ) vreflr( a 7,a8 ) v refhr(a5 , a6 ) d if0/dzfl(d1 ) d if1/dzfr(c1 ) d em0/dsdl(b1 ) s d/cclk/scl(e2 ) p dn(h2 ) s slow/wck(g2 ) t dmo(f2 ) gain/dsdr(b 2 ) t dm0/dclk(a3 ) e xtr(j5 ) vdd1 v ss1 vss 0v a vdd 1.8v vdd2 0.1 ? f 0.1 ? f 1 ? f 0.1 ? f 0.1 ? f cad1 cad0 vdd3 vss2 v dd 4 vss3 0.1 ? f 0.1 ? f vss 0v 33kohm external lpf circuit aoutr 1 ? f 1 ? f external lpf circuit aoutl 1 ? f vdd 5v 1 ? f power supply 6v e xternal regulator circuit e xternal regulator circuit
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 98 - 5 . connection example with the ak 4205 the ak4205 is a low - di storsion stereo headphon e amplifier with an analog switch for hi - fi mobile a plications . it integrates a gain setting resistor and a lpf, saving mounting area of the printing circuit board. a connection example of the ak4492 and the ak44205 is shown below. exposed pad (tab) on the bottom surface of the package should be connected t o the gorund. system rayout should be designed so that a noise interference between vss and dvss does not occure . the ak8175a can be connected at the input stage of the ak4492 ( figure 75 ). figure 76 . circuit example with ak4205 power supply 6 v power supply - 5v css= 0.1u rd 33 a k4205 top view headphone r ch headphone l ch aux in (rch) aux in (lch) 0.1u 10u 0.1u 10u 0.1u 0.1u 10u 10u rd 33 1 0 u 1 0 u 0. 1u 0. 1u dc 2.5v dc 2.5v dc 2.5v dc 2.5v d vss 0v dvdd 1.8v vss dvss 0.1 ? f vss 0v bick sdata lrck mcl k b ick/bck/dclk(j1 ) s data/dinl/dsdl(h1 ) lrck/dinr/dsdr( g1 ) s low/cdti/sda(e1 ) d vss(k2 ) t vdd(j2 ) d if2/cad0(d2 ) h load/i2c(c2 ) a cks/cad1(a2 ) d vdd(k3 ) l doe(h 3 ) p sn(d3) t dm1(b3 ) a vdd(k4 ) a vss(j4 ) d chain(b4 ) i nvr(a4 ) a k4492 s mute/csn(f1 ) mclk( j3 ) t este(b5 ) a outrp(b 9) a outrn(a9 ) v ssr(d10,e9,e10 ) v ddr(c9 , c10 , d9 ) vrefhl( k5 , k6 ) v refll(l7,k8 ) v cml(j8 ) aoutln( k9 ) aoutlp(j 9 ) v ddl(g9,h9,h10 ) v ssl(f9,f10,g10 ) v cmr(b8 ) vreflr( a7,a8 ) v refhr(a5 , a6 ) d if0/dzfl(d1 ) s slow/wck(g2 ) t dmo(f2 ) gain/dsdr(b 2 ) t dm0/dclk(a3 ) e xtr(j5 ) 0.1 ? f 0.1 ? f 1 ? f s d/cclk/scl( e2 ) p dn(h2 ) d if1/dzfr(c1 ) d em0/dsdl(b1 ) 51ohm 33kohm 1 ? f 1 ? f 1 ? f vdd 5v acpu 1 ? f swvdd 3.3v e x ternal regulator circuit swout a nc nc capss swvdd swvss swout b sel nc nc pvee b ampout b pvdd b nc aux b muten rstn pvee a ampout a pvdd a nc nc swin a pin a avssa nc rvdd rvss avss b pin b nin b 36 35 34 26 25 24 23 22 21 20 19 33 32 31 30 29 10 11 12 13 14 15 16 17 28 nin a 27 aux a 18 nc swin b nc 1 2 3 4 5 6 7 8 9 tab nc a k4205 e xternal regulator circuit 470n 470n 5v rwm zener diode 5v rwm zener diode dc 0v dc 0v
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 99 - 11. package outline dimensions ( 96 - pin wlcsp ) material & lead finish package molding compound : halogen free solder ball material : sac - 405 (sn/ a g /cu ) marking 1) akm logo 2) pin #a1 indication 3) date code: xxxx (4 digits) 4) ma rking code: ak4492 x x x x k a m a k 4 4 9 2
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 100 - 12. ordering guide ordering guide ak4492 ecb ? 40 ? +85 ? c 96 - pin wlcsp akd449 2 ak449 2 evaluation board 13. revesion history date (y/m/d) revision reason page contents 1 6 / 12 / 1 00 first edition
[ ak449 2 ] 016011073 - e - 00 2016/1 2 - 101 - important n otice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes w arranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above us e unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, s oftware and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile t echnology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact ak m sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, includi ng without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liabi lity of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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